公开(公告)号：US11152517B2

公开(公告)日：2021-10-19

申请号：US16734537

申请日：2020-01-06

Applicant: Samsung Electronics Co., Ltd.

Inventor： Sunguk Jang ,  Kihwan Kim ,  Sujin Jung ,  Youngdae Cho

IPC: H01L29/08 ,  H01L29/786 ,  H01L29/423 ,  H01L29/78 ,  H01L29/06 ,  H01L29/66

Abstract: A semiconductor device includes an active region on a substrate extending in a first direction, the active region having an upper surface and sidewalls, a plurality of channel layers above the active region to be vertically spaced apart from each other, a gate electrode extending in a second direction to intersect the active region and partially surrounding the plurality of channel layers, and a source/drain region on the active region on at least one side of the gate electrode and in contact with the plurality of channel layers, and extending from the sidewalls of the active region having a major width in the second direction in a first region adjacent to a lowermost channel layer adjacent to the active region among the plurality of channel layer.

公开(公告)号：US10062754B2

公开(公告)日：2018-08-28

申请号：US14491117

申请日：2014-09-19

Applicant: Samsung Electronics Co., Ltd.

Inventor： Jinbum Kim ,  Bonyoung Koo ,  Seokhoon Kim ,  Chul Kim ,  Kwan Heum Lee ,  Byeongchan Lee ,  Sujin Jung

IPC: H01L29/78 ,  H01L29/08 ,  H01L29/66 ,  H01L21/306 ,  H01L21/3065 ,  H01L29/165

CPC classification number: H01L29/0847 ,  H01L21/30608 ,  H01L21/3065 ,  H01L29/165 ,  H01L29/66545 ,  H01L29/66795 ,  H01L29/7848 ,  H01L29/785

Abstract: A semiconductor device includes a substrate provided with an active pattern; a gate structure provided on the active pattern to cross the active pattern; and source/drain regions provided at both sides of the gate structure. The active pattern includes a first region below the gate structure and second regions at both sides of the gate structure. A top surface of each of the second regions is lower than that of the first region. The source/drain regions are provided on the second regions, respectively, and each of the source/drain regions covers partially both sidewalls of each of the second regions.

公开(公告)号：US09899497B2

公开(公告)日：2018-02-20

申请号：US15355781

申请日：2016-11-18

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Jin Bum Kim ,  Kang Hun Moon ,  Choeun Lee ,  Kyung Yub Jeon ,  Sujin Jung ,  Haegeon Jung ,  Yang Xu

IPC: H01L29/66 ,  H01L29/08 ,  H01L21/306 ,  H01L21/02

CPC classification number: H01L29/66795 ,  H01L21/02381 ,  H01L21/0243 ,  H01L21/02433 ,  H01L21/02532 ,  H01L21/30604 ,  H01L29/0847 ,  H01L29/66545 ,  H01L29/66636 ,  H01L29/7848

Abstract: A method of fabricating a semiconductor device is disclosed. The method includes forming an active pattern protruding orthogonally from a substrate; forming a preliminary gate structure on the active pattern to cross the active pattern; etching the active pattern to form preliminary recess regions at both sides of the preliminary gate structure, wherein each of the preliminary recess regions is formed to define a delta region in an upper portion of the active pattern; forming a sacrificial layer on inner side surfaces and a bottom surface of the active pattern exposed by each of the preliminary recess regions; etching the delta regions and the sacrificial layer to form recess regions having a ‘U’-shaped section; and forming source/drain regions in the recess regions.

公开(公告)号：US09530870B2

公开(公告)日：2016-12-27

申请号：US14805876

申请日：2015-07-22

Applicant: Samsung Electronics Co., Ltd.

Inventor： Jieon Yoon ,  Seokhoon Kim ,  Gyeom Kim ,  Nam-Kyu Kim ,  JinBum Kim ,  Dong Chan Suh ,  Kwan Heum Lee ,  Byeongchan Lee ,  Choeun Lee ,  Sujin Jung

IPC: H01L29/66 ,  H01L29/78 ,  H01L29/08 ,  H01L21/306 ,  H01L21/8234 ,  H01L21/324 ,  H01L29/04 ,  H01L21/265 ,  H01L29/165

CPC classification number: H01L29/66795 ,  H01L21/26506 ,  H01L21/30608 ,  H01L21/3247 ,  H01L21/823425 ,  H01L29/045 ,  H01L29/0847 ,  H01L29/165 ,  H01L29/6656 ,  H01L29/66636 ,  H01L29/7848

Abstract: Provided is a method of fabricating a semiconductor device. The method includes forming a gate pattern on a semiconductor substrate, injecting amorphization elements into the semiconductor substrate to form an amorphous portion at a side of the gate pattern, removing the amorphous portion to form a recess region, and forming a source/drain pattern in the recess region. When the recess region is formed, an etch rate of the amorphous portion is substantially the same in two different directions (e.g., and any other direction) of the semiconductor substrate.

Abstract translation: 提供一种制造半导体器件的方法。 该方法包括在半导体衬底上形成栅极图案，将非晶化元件注入到半导体衬底中以在栅极图案的一侧形成非晶部分，去除非晶部分以形成凹陷区域，并且形成源极/漏极图案 凹陷区域。 当形成凹陷区域时，非晶部分的蚀刻速率在半导体衬底的两个不同方向（例如，<111>和任何其它方向）上基本相同。

公开(公告)号：US09412731B2

公开(公告)日：2016-08-09

申请号：US14562788

申请日：2014-12-08

Applicant: Samsung Electronics Co., Ltd.

Inventor： Seokhoon Kim ,  Bonyoung Koo ,  JinBum Kim ,  Chul Kim ,  Kwan Heum Lee ,  Byeongchan Lee ,  Sujin Jung

IPC: H01L29/78 ,  H01L27/02 ,  H01L29/06 ,  H01L27/088

CPC classification number: H01L27/0207 ,  H01L21/823431 ,  H01L27/0886 ,  H01L29/0649 ,  H01L29/66545 ,  H01L29/7834 ,  H01L29/7848

Abstract: Provided is a semiconductor device which includes a substrate including a first region and a second region different from the first region, a first active pattern provided on the substrate in the first region, a second active pattern provided on the substrate in the second region, a first gate structure crossing over the first active pattern and a second gate structure crossing over the second active pattern, first source/drain regions disposed on the first active pattern at opposite sides of the first gate structure, second source/drain regions disposed on the second active pattern at opposite sides of the second gate structure, and auxiliary spacers disposed in the first region to cover a lower portion of each of the first source/drain regions.

Abstract translation: 提供一种半导体器件，其包括：衬底，其包括第一区域和与第一区域不同的第二区域;设置在第一区域中的衬底上的第一有源图案，设置在第二区域中的衬底上的第二有源图案; 在第一有源图案上交叉的第一栅极结构和与第二有源图案交叉的第二栅极结构，在第一栅极结构的相对侧设置在第一有源图案上的第一源/漏区，设置在第二有源图案上的第二栅极结构的第二栅极结构 在第二栅极结构的相对侧的有源图案以及设置在第一区域中以覆盖每个第一源极/漏极区域的下部的辅助间隔物。

公开(公告)号：US20250120121A1

公开(公告)日：2025-04-10

申请号：US18733327

申请日：2024-06-04

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Unki KIM ,  Kihwan Kim ,  Chanyoung Kim ,  Jeongho Yoo ,  Ingyu Jang ,  Sujin Jung

IPC: H01L29/786 ,  H01L29/06 ,  H01L29/16 ,  H01L29/167 ,  H01L29/423 ,  H01L29/66 ,  H01L29/775

Abstract: A semiconductor memory device is provided. The semiconductor memory device includes: a substrate; an active region extending in a first direction on the substrate; a plurality of channel layers stacked on the active region and spaced apart from each other in a vertical direction perpendicular to the first direction; a gate structure extending on the active region in a second direction perpendicular to the first direction and the vertical direction, and surrounding the plurality of channel layers; a source/drain region provided on at least one side of the gate structure on the active region and electrically connected to the plurality of channel layers; and a plurality of anti-diffusion layers stacked and spaced apart from each other in the vertical direction and extending in the second direction.

公开(公告)号：US12268022B2

公开(公告)日：2025-04-01

申请号：US17714695

申请日：2022-04-06

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Jinbum Kim ,  Dahye Kim ,  Dongmyoung Kim ,  Dongwoo Kim ,  Yongjun Nam ,  Sangmoon Lee ,  Ingyu Jang ,  Sujin Jung

IPC: H10D62/10 ,  H10D62/13 ,  H10D62/17

Abstract: A semiconductor device includes a substrate having an active region extending in a first direction; a gate structure disposed on the substrate, intersecting the active region, and extending in a second direction; channel layers disposed on the active region to be spaced apart from each other in a third direction, perpendicular to an upper surface of the substrate, and to be surrounded by the gate structure; source/drain regions disposed on both sides of the gate structure and connected to the channel layers; air gap regions located between the source/drain regions and the active region and spaced apart from each other in the third direction; and semiconductor layers alternately disposed with the air gap regions in the third direction and defining the air gap regions, wherein lower ends of the source/drain regions are located on a level lower than an uppermost air gap region.

公开(公告)号：US12087766B2

公开(公告)日：2024-09-10

申请号：US17383749

申请日：2021-07-23

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Sujin Jung ,  Kihwan Kim ,  Sunguk Jang ,  Youngdae Cho

IPC: H01L27/088 ,  H01L29/06 ,  H01L29/78

CPC classification number: H01L27/0886 ,  H01L29/0669 ,  H01L29/7851

Abstract: An integrated circuit (IC) device includes a fin-type active region extending longitudinally in a first lateral direction on a substrate. A nanosheet is apart from a fin top surface of the fin-type active region in a vertical direction. An inner insulating spacer is between the substrate and the nanosheet. A gate line includes a main gate portion and a sub-gate portion. The main gate portion extends longitudinally in a second lateral direction on the nanosheet. The sub-gate portion is integrally connected to the main gate portion and between the substrate and the nanosheet. A source/drain region is in contact with the inner insulating spacer and the nanosheet. The source/drain region includes a single crystalline semiconductor body and at least one lower stacking fault surface linearly extending from the inner insulating spacer through the single crystalline semiconductor body.

公开(公告)号：US20240145542A1

公开(公告)日：2024-05-02

申请号：US18325412

申请日：2023-05-30

Applicant: SAMSUNG ELECTRONICS CO, LTD.

Inventor： Jang Ingyu ,  Jinbum Kim ,  Sujin Jung ,  Gyeom Kim ,  Dahye Kim

IPC: H01L29/06 ,  H01L29/423 ,  H01L29/45 ,  H01L29/775 ,  H01L29/786

CPC classification number: H01L29/0673 ,  H01L29/42392 ,  H01L29/45 ,  H01L29/775 ,  H01L29/78696

Abstract: A semiconductor device includes an active pattern disposed on a substrate; a gate structure disposed on the active pattern; channels disposed on the substrate and that are spaced apart from each other in a vertical direction substantially perpendicular to an upper surface of the substrate; a first epitaxial layer disposed on a portion of the active pattern adjacent to the gate structure; and a contact plug disposed on the first epitaxial layer. The contact plug includes a lower portion; a middle portion disposed on the lower portion, where the middle portion has a width that increases from a bottom to a top thereof along the vertical direction; and an upper portion disposed on the middle portion.

公开(公告)号：US11881510B2

公开(公告)日：2024-01-23

申请号：US17935561

申请日：2022-09-26

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Jinbum Kim ,  Seokhoon Kim ,  Kwanheum Lee ,  Choeun Lee ,  Sujin Jung

IPC: H01L29/08 ,  H01L29/78 ,  H01L29/167 ,  H01L29/786 ,  H01L29/06 ,  H01L29/423

CPC classification number: H01L29/0847 ,  H01L29/0653 ,  H01L29/167 ,  H01L29/785 ,  H01L29/78696 ,  H01L29/0673 ,  H01L29/42392

Abstract: A semiconductor device includes a channel, a first source/drain structure on a first side surface of the channel, a second source/drain structure on a second side surface of the channel, a gate structure surrounding the channel, an inner spacer layer on a side surface of the gate structure, and an outer spacer layer on an outer surface of the inner spacer layer. The first source/drain structure includes a first source/drain layer on the channel and a second source/drain layer on the first source/drain layer, and on a plane of the semiconductor device that passes through the channel, at least one of a first boundary line of the first source/drain layer in contact with the second source/drain layer and a second boundary line of the first source/drain layer in contact with the channel may be convex, extending toward the channel.