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公开(公告)号：US12237046B2
公开(公告)日：2025-02-25
申请号：US17951567
申请日：2022-09-23
Applicant: Samsung Electronics Co., Ltd.
Inventor： Youngmin Jo , Tongsung Kim , Chiweon Yoon , Byunghoon Jeong
Abstract: A memory system includes a plurality of memory devices, each connected to internal channels respectively including an internal data channel and an internal control channel, and each configured to perform communication based on a first interface protocol, a controller connected to an external channel including an external data channel and an external control channel and configured to perform communication based on a second interface protocol, and an interface circuit connecting the external channel to each of the internal channels. The interface circuit is configured to perform channel conversion by serializing a parallel data signal received from the controller through the external data channel and outputting the serialized signal to the internal control channel included in a first one of the internal channels, or parallelizing a signal received through the external control channel and outputting the parallelized signal to the internal data channel included in the first one of the internal channels.
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公开(公告)号：US12112071B2
公开(公告)日：2024-10-08
申请号：US18217063
申请日：2023-06-30
Applicant: Samsung Electronics Co., Ltd.
Inventor： Seonkyoo Lee , Jeongdon Ihm , Chiweon Yoon , Byunghoon Jeong
CPC classification number: G06F3/0659 , G06F1/06 , G06F3/0613 , G06F3/0679 , G06F13/1668 , G11C16/0483 , G11C16/10 , G11C16/26
Abstract: A nonvolatile memory device includes a first pin that receives a first signal, a second pin that receives a second signal, third pins that receive third signals, a fourth pin that receives a write enable signal, a memory cell array, and a memory interface circuit that obtains a command, an address, and data from the third signals in a first mode and obtains the command and the address from the first signal and the second signal and the data from the third signals in a second mode. In the first mode, the memory interface circuit obtains the command from the third signals and obtains the address from the third signals. In the second mode, the memory interface circuit obtains the command from the first signal and the second signal and obtains the address from the first signal and the second signal.
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公开(公告)号：US12047082B2
公开(公告)日：2024-07-23
申请号：US17994296
申请日：2022-11-26
Applicant: Samsung Electronics Co., Ltd.
Inventor： Anil Kavala , Seonkyoo Lee , Taesung Lee , Jeongdon Ihm , Byunghoon Jeong
CPC classification number: H03L7/0816 , G11C7/222 , H03K5/133 , H03L7/085 , G11C29/023 , G11C29/028
Abstract: A semiconductor device includes an internal clock generation circuit configured to generate an internal clock; a plurality of unit circuits configured to have a first unit circuit and a second unit circuit operating while being synchronized with an internal clock; a plurality of transfer circuits including a first transfer circuit configured to provide a first transfer path having a first delay time, and a second transfer circuit configured to provide a second transfer path having a second delay time different from the first delay time; and a delay compensation circuit configured to compare a first clock input to the first unit circuit through the first transfer path with a second clock input to the second unit circuit through the second transfer path, and to adjust the second delay time so that the adjusted second delay time matches the first delay time.
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公开(公告)号：US12008268B2
公开(公告)日：2024-06-11
申请号：US17867008
申请日：2022-07-18
Applicant: Samsung Electronics Co., Ltd.
Inventor： Daehoon Na , Jeongdon Ihm , Jangwoo Lee , Byunghoon Jeong
CPC classification number: G06F3/0659 , G06F1/06 , G06F3/0611 , G06F3/0656 , G06F3/0679 , G11C16/10 , G11C16/26 , G11C16/32 , G11C16/0483
Abstract: A memory system includes a memory device including a plurality of non-volatile memories and an interface circuit connected to each of the plurality of non-volatile memories, and a memory controller connected to the interface circuit and configured to transmit/receive data according to a first clock, wherein the interface circuit is configured to divide the first clock into a second clock, according to the number of the plurality of non-volatile memories, and transmit/receive data to/from each of the plurality of non-volatile memories, according to the second clock.
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公开(公告)号：US11915781B2
公开(公告)日：2024-02-27
申请号：US17938214
申请日：2022-10-05
Applicant: SAMSUNG ELECTRONICS CO., LTD.
Inventor： Dongho Shin , Jungjune Park , Kyoungtae Kang , Chiweon Yoon , Junha Lee , Byunghoon Jeong
CPC classification number: G11C7/1051 , H03K19/0005 , G11C2207/2254
Abstract: An apparatus and method for ZQ calibration, including determining a strong driver circuit and a weak driver circuit, which are related to an input/output (I/O) circuit connected to a signal pin, at power-up of the I/O circuit; providing a ZQ calibration code related to a sweep code to one from among the strong driver circuit and the weak driver circuit according to ZQ calibration conditions; and providing a ZQ calibration code related to a fixed code to an unselected circuit, thereby adjusting a termination resistance of the signal pin.
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Patent Agency Ranking
公开(公告)号：US20230162766A1
公开(公告)日：2023-05-25
申请号：US17951567
申请日：2022-09-23
Applicant: Samsung Electronics Co., Ltd.
Inventor： Youngmin Jo , Tongsung Kim , Chiweon Yoon , Byunghoon Jeong
CPC classification number: G11C7/1087 , G11C7/109 , G11C7/1093 , G11C7/222
Abstract: A memory system includes a plurality of memory devices, each connected to internal channels respectively including an internal data channel and an internal control channel, and each configured to perform communication based on a first interface protocol, a controller connected to an external channel including an external data channel and an external control channel and configured to perform communication based on a second interface protocol, and an interface circuit connecting the external channel to each of the internal channels. The interface circuit is configured to perform channel conversion by serializing a parallel data signal received from the controller through the external data channel and outputting the serialized signal to the internal control channel included in a first one of the internal channels, or parallelizing a signal received through the external control channel and outputting the parallelized signal to the internal data channel included in the first one of the internal channels.
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公开(公告)号：US11475955B2
公开(公告)日：2022-10-18
申请号：US17393784
申请日：2021-08-04
Applicant: Samsung Electronics Co., Ltd.
Inventor： Junha Lee , Seonkyoo Lee , Jeongdon Ihm , Byunghoon Jeong
IPC: G11C16/06 , H01L23/66 , H01L25/065 , H01L25/18 , H01L23/00
Abstract: A multi-chip package with reduced calibration time and an impedance control (ZQ) calibration method thereof are provided. A master chip of the multi-chip package performs a first ZQ calibration operation by using a ZQ resistor, and then, the other slave chips simultaneously perform second ZQ calibration operations with respect to data input/output (DQ) pads of the slave chips by using a termination resistance value of a DQ pad of the master chip on the basis of a one-to-one correspondence relationship with the DQ pad of the master chip. The multi-chip package completes ZQ calibration by performing two ZQ calibration operations, thereby decreasing a ZQ calibration time.
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公开(公告)号：US11367471B2
公开(公告)日：2022-06-21
申请号：US17352527
申请日：2021-06-21
Applicant: Samsung Electronics Co., Ltd.
Inventor： Anil Kavala , Tongsung Kim , Chiweon Yoon , Byunghoon Jeong
IPC: G11C7/10 , H03K19/00 , H01L27/115 , G11C16/04
Abstract: An impedance calibration circuit includes a first variable impedance, a second variable impedance, a third variable impedance. The first variable impedance is connected to a ZQ terminal. A first control circuit performs a first impedance calibration on the first variable impedance based on an output signal from an output of a first comparator. A second control circuit performs a second impedance calibration on the third variable impedance based on an output signal from an output of a second comparator. A first switch connects an input of the first comparator to one of the ZQ terminal and the first node. A second switch connects the output of the first comparator to one of the first and second control circuits. A third switch connects an output of the first switch to one of first and second input terminals of the first comparator and connects the reference voltage to the other.
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公开(公告)号：US20220101894A1
公开(公告)日：2022-03-31
申请号：US17410210
申请日：2021-08-24
Applicant: SAMSUNG ELECTRONICS CO., LTD.
Inventor： Seonkyoo Lee , Chiweon Yoon , Byunghoon Jeong , Youngmin Jo
IPC: G11C7/10 , H01L25/065
Abstract: An operating method of a memory device includes selecting a receiver from a plurality of receivers of each memory chip of a plurality of memory chips included in the memory device as a first receiver. The plurality of memory chips share a plurality of data signal lines, each memory chip includes a plurality of on-die termination (ODT) resistors, and the plurality of ODT resistors are respectively connected to the plurality of receivers of each memory chip. The method further includes setting each ODT resistor which is connected to a first receiver to a first resistance value, setting ODT resistors which are connected to receivers which are not first receivers to a second resistance value, and setting an amplification strength of an equalizer circuit of each first receiver by performing training operations. Each data signal line of the plurality of data signal lines is respectively connected to a first receiver.
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公开(公告)号：US11217283B2
公开(公告)日：2022-01-04
申请号：US17012845
申请日：2020-09-04
Applicant: Samsung Electronics Co., Ltd.
Inventor： Junha Lee , Seonkyoo Lee , Jeongdon Ihm , Byunghoon Jeong
IPC: G11C7/10 , H01L25/065 , H01L25/18 , H01L23/00
Abstract: A multi-chip package with reduced calibration time and an impedance control (ZQ) calibration method thereof are provided. A master chip of the multi-chip package performs a first ZQ calibration operation by using a ZQ resistor, and then, the other slave chips simultaneously perform second ZQ calibration operations with respect to data input/output (DQ) pads of the slave chips by using a termination resistance value of a DQ pad of the master chip on the basis of a one-to-one correspondence relationship with the DQ pad of the master chip. The multi-chip package completes ZQ calibration by performing two ZQ calibration operations, thereby decreasing a ZQ calibration time.
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