公开(公告)号：US09082874B2

公开(公告)日：2015-07-14

申请号：US14565922

申请日：2014-12-10

Applicant: Samsung Electronics Co., Ltd.

Inventor： Dong Hyuk Kim ,  Dongsuk Shin ,  Hoi Sung Chung ,  Naein Lee

IPC: H01L21/336 ,  H01L21/8234 ,  H01L29/04 ,  H01L21/306 ,  H01L21/02 ,  H01L21/324 ,  H01L29/78

CPC classification number: H01L21/823437 ,  H01L21/02636 ,  H01L21/30608 ,  H01L21/324 ,  H01L21/823481 ,  H01L21/84 ,  H01L29/045 ,  H01L29/165 ,  H01L29/665 ,  H01L29/66636 ,  H01L29/78 ,  H01L29/7834 ,  H01L29/7843 ,  H01L29/7848

Abstract: A semiconductor device includes a gate pattern disposed on a semiconductor substrate, a bulk epitaxial pattern disposed in a recess region formed in the semiconductor substrate at a side of the gate pattern, an insert epitaxial pattern disposed on the bulk epitaxial pattern, and a capping epitaxial pattern disposed on the insert epitaxial pattern. The bulk epitaxial pattern has an upper inclined surface that is a {111} crystal plane, and the insert epitaxial pattern includes a specific element that promotes the growth rate of the insert epitaxial pattern on the upper inclined surface.

Abstract translation: 半导体器件包括设置在半导体衬底上的栅极图案，设置在形成在栅极图案侧的半导体衬底中的凹陷区域中的体外延图案，设置在整体外延图案上的插入外延图案和封盖外延 图案设置在插入物外延图案上。 本体外延图案具有为{111}晶面的上倾斜面，并且插入物外延图案包括促进插入物外延图案在上倾斜表面上的生长速率的特定元件。

公开(公告)号：US08937343B2

公开(公告)日：2015-01-20

申请号：US14021469

申请日：2013-09-09

Applicant: Samsung Electronics Co., Ltd.

Inventor： Dong Hyuk Kim ,  Dongsuk Shin ,  Hoi Sung Chung ,  Naein Lee

IPC: H01L29/78 ,  H01L29/04 ,  H01L21/84 ,  H01L29/66

CPC classification number: H01L21/823437 ,  H01L21/02636 ,  H01L21/30608 ,  H01L21/324 ,  H01L21/823481 ,  H01L21/84 ,  H01L29/045 ,  H01L29/165 ,  H01L29/665 ,  H01L29/66636 ,  H01L29/78 ,  H01L29/7834 ,  H01L29/7843 ,  H01L29/7848

Abstract: A semiconductor device includes a gate pattern disposed on a semiconductor substrate, a bulk epitaxial pattern disposed in a recess region formed in the semiconductor substrate at a side of the gate pattern, an insert epitaxial pattern disposed on the bulk epitaxial pattern, and a capping epitaxial pattern disposed on the insert epitaxial pattern. The bulk epitaxial pattern has an upper inclined surface that is a {111} crystal plane, and the insert epitaxial pattern includes a specific element that promotes the growth rate of the insert epitaxial pattern on the upper inclined surface.

公开(公告)号：US20140087537A1

公开(公告)日：2014-03-27

申请号：US13949303

申请日：2013-07-24

Applicant: Samsung Electronics Co., Ltd.

Inventor： Dong Hyuk Kim ,  Hoi Sung Chung ,  Dongsuk Shin ,  Naein Lee

IPC: H01L29/66

CPC classification number: H01L29/7833 ,  H01L29/045 ,  H01L29/0847 ,  H01L29/165 ,  H01L29/66477 ,  H01L29/66636 ,  H01L29/7834 ,  H01L29/7848

Abstract: A semiconductor device including source drain stressors and methods of manufacturing the same are provided. The methods may include forming a recess region in the substrate at a side of a gate pattern, and an inner surface of the recess region may include a first surface of a (100) crystal plane and a second surface of one of {111} crystal planes. The method may further include performing a first selective epitaxial growth (SEG) process to form a base epitaxial pattern on the inner surface of the recess region at a process pressure in a range of about 50 Torr to about 300 Torr. The method may also include performing a second selective epitaxial growth (SEG) process to form a bulk epitaxial pattern on the base epitaxial pattern.

Abstract translation: 提供了包括源漏应力源的半导体器件及其制造方法。 所述方法可以包括在栅极图案侧的基板中形成凹陷区域，并且凹部区域的内表面可以包括（100）晶面的第一表面和{111}晶体之一的第二表面 飞机 该方法还可以包括执行第一选择性外延生长（SEG）工艺，以在约50托至约300托的范围内的工艺压力下在凹陷区的内表面上形成基底外延图案。 该方法还可以包括执行第二选择性外延生长（SEG）工艺以在基底外延图案上形成体外延图案。

公开(公告)号：US12159911B2

公开(公告)日：2024-12-03

申请号：US17552446

申请日：2021-12-16

Applicant: Samsung Electronics Co., Ltd.

Inventor： Gyeom Kim ,  Jinbum Kim ,  Dongwoo Kim ,  Dongsuk Shin ,  Sangmoon Lee ,  Seung Hun Lee

IPC: H01L29/41 ,  H01L21/02 ,  H01L27/092 ,  H01L29/06 ,  H01L29/40 ,  H01L29/417 ,  H01L29/423 ,  H01L29/66 ,  H01L29/78 ,  H01L29/786

Abstract: A semiconductor device includes a substrate including an active pattern, a channel pattern and a source/drain pattern on the active pattern, a gate electrode provided on the channel pattern and extended in a first direction, and an active contact coupled to the source/drain pattern. The active contact includes a buried portion buried in the source/drain pattern and a contact portion on the buried portion. The buried portion includes an expansion portion provided in a lower portion of the source/drain pattern and a vertical extension portion connecting the contact portion to the expansion portion.

公开(公告)号：US11653308B2

公开(公告)日：2023-05-16

申请号：US17408700

申请日：2021-08-23

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Junghun Heo ,  Youngduk Kim ,  Joonseok Kim ,  Dongsuk Shin

IPC: G06F1/32 ,  H04W52/02

CPC classification number: H04W52/0287 ,  G06F1/32 ,  H04W52/0261 ,  Y02D30/70

Abstract: A power management approach for a mobile device includes comparing a battery provided power supply voltage to a reference voltage in order to generate an alarm signal. In response to the alarm signal the frequency of an operating clock applied to a system-on-chip is changed.

公开(公告)号：US11171224B2

公开(公告)日：2021-11-09

申请号：US16889899

申请日：2020-06-02

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Dong Chan Suh ,  Sangmoon Lee ,  Yihwan Kim ,  Woo Bin Song ,  Dongsuk Shin ,  Seung Ryul Lee

IPC: H01L29/66 ,  H01L21/28 ,  H01L29/786 ,  H01L29/423 ,  H01L29/78

Abstract: A method for manufacturing a semiconductor device and a semiconductor device, the method including forming an active pattern on a substrate such that the active pattern includes sacrificial patterns and semiconductor patterns alternately and repeatedly stacked on the substrate; and forming first spacer patterns at both sides of each of the sacrificial patterns by performing an oxidation process, wherein the first spacer patterns correspond to oxidized portions of each of the sacrificial patterns, wherein the sacrificial patterns include a first semiconductor material containing impurities, wherein the semiconductor patterns include a second semiconductor material different from the first semiconductor material, and wherein the impurities include an element different from semiconductor elements of the first semiconductor material and the second semiconductor material.

公开(公告)号：US10756211B2

公开(公告)日：2020-08-25

申请号：US15379190

申请日：2016-12-14

Applicant: Samsung Electronics Co., Ltd.

Inventor： Keum Seok Park ,  Jungho Yoo ,  Jinyeong Joe ,  Bonyoung Koo ,  Dongsuk Shin ,  Hongsik Yoon ,  Byeongchan Lee

IPC: H01L29/78 ,  H01L29/165 ,  H01L29/66 ,  H01L21/02 ,  H01L29/06 ,  H01L29/08 ,  H01L29/45

Abstract: A semiconductor device includes an active pattern protruding from a substrate, a gate structure crossing over the active pattern, and source/drain regions disposed on the active pattern at opposite sides of the gate structure. Each of the source/drain regions includes a first epitaxial pattern contacting the active pattern and a second epitaxial pattern on the first epitaxial pattern. The first epitaxial pattern comprises a material having a lattice constant which is the same as that of the substrate, and the second epitaxial pattern comprises a material having a lattice constant greater than that of the first epitaxial pattern.

公开(公告)号：US09553190B2

公开(公告)日：2017-01-24

申请号：US14673519

申请日：2015-03-30

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Keum Seok Park ,  Jungho Yoo ,  Jinyeong Joe ,  Bonyoung Koo ,  Dongsuk Shin ,  Hongsik Yoon ,  Byeongchan Lee

IPC: H01L29/772 ,  H01L29/417 ,  H01L29/78 ,  H01L29/66 ,  H01L29/165

CPC classification number: H01L29/7848 ,  H01L21/02532 ,  H01L21/02636 ,  H01L29/0649 ,  H01L29/0847 ,  H01L29/165 ,  H01L29/45 ,  H01L29/66545 ,  H01L29/785

Abstract: A semiconductor device includes an active pattern protruding from a substrate, a gate structure crossing over the active pattern, and source/drain regions disposed on the active pattern at opposite sides of the gate structure. Each of the source/drain regions includes a first epitaxial pattern contacting the active pattern and a second epitaxial pattern on the first epitaxial pattern. The first epitaxial pattern comprises a material having a lattice constant which is the same as that of the substrate, and the second epitaxial pattern comprises a material having a lattice constant greater than that of the first epitaxial pattern.

Abstract translation: 半导体器件包括从衬底突出的有源图案，在有源图案上交叉的栅极结构以及设置在栅极结构的相对侧上的有源图案上的源极/漏极区域。 源极/漏极区域中的每一个包括接触有源图案的第一外延图案和第一外延图案上的第二外延图案。 第一外延图案包括具有与衬底相同的晶格常数的材料，并且第二外延图案包括具有大于第一外延图案的晶格常数的晶格常数的材料。

公开(公告)号：US20160111538A1

公开(公告)日：2016-04-21

申请号：US14969702

申请日：2015-12-15

Applicant: Samsung Electronics Co., Ltd.

Inventor： Donghyun Roh ,  Pankwi Park ,  Dongsuk Shin ,  Chulwoong Lee ,  Naein Lee

IPC: H01L29/78 ,  H01L29/165 ,  H01L29/161

CPC classification number: H01L29/7849 ,  H01L21/30604 ,  H01L21/76224 ,  H01L21/823412 ,  H01L21/823418 ,  H01L21/823468 ,  H01L21/823481 ,  H01L29/0649 ,  H01L29/161 ,  H01L29/165 ,  H01L29/42376 ,  H01L29/66477 ,  H01L29/66553 ,  H01L29/7848

Abstract: According to embodiments of the inventive concept, a gate electrode is formed on a substrate, and a first spacer, a second spacer, and a third spacer are sequentially formed on a sidewall of the gate electrode. The substrate is etched to form a recess region. A compressive stress pattern is formed in the recess region. A protective spacer is formed on a sidewall of the third spacer. When the recess region is formed, a lower portion of the second spacer is removed to form a gap region between the first and third spacers. The protective spacer fills the gap region.

Abstract translation: 根据本发明构思的实施例，栅极形成在衬底上，并且第一间隔物，第二间隔物和第三间隔物依次形成在栅电极的侧壁上。 蚀刻衬底以形成凹陷区域。 在凹部形成压缩应力图形。 在第三间隔件的侧壁上形成保护隔离件。 当形成凹陷区域时，去除第二间隔物的下部以在第一和第三间隔物之间​​形成间隙区域。 保护性间隔物填充间隙区域。

公开(公告)号：US09252235B2

公开(公告)日：2016-02-02

申请号：US13957912

申请日：2013-08-02

Applicant: Samsung Electronics Co., Ltd.

Inventor： Donghyun Roh ,  Pankwi Park ,  Dongsuk Shin ,  Chulwoong Lee ,  Naein Lee

IPC: H01L21/76 ,  H01L29/66 ,  H01L21/8234

CPC classification number: H01L29/7849 ,  H01L21/30604 ,  H01L21/76224 ,  H01L21/823412 ,  H01L21/823418 ,  H01L21/823468 ,  H01L21/823481 ,  H01L29/0649 ,  H01L29/161 ,  H01L29/165 ,  H01L29/42376 ,  H01L29/66477 ,  H01L29/66553 ,  H01L29/7848

Abstract: According to embodiments of the inventive concept, a gate electrode is formed on a substrate, and a first spacer, a second spacer, and a third spacer are sequentially formed on a sidewall of the gate electrode. The substrate is etched to form a recess region. A compressive stress pattern is formed in the recess region. A protective spacer is formed on a sidewall of the third spacer. When the recess region is formed, a lower portion of the second spacer is removed to form a gap region between the first and third spacers. The protective spacer fills the gap region.

Abstract translation: 根据本发明构思的实施例，栅极形成在衬底上，并且第一间隔物，第二间隔物和第三间隔物依次形成在栅电极的侧壁上。 蚀刻衬底以形成凹陷区域。 在凹部形成压缩应力图形。 在第三间隔件的侧壁上形成保护隔离件。 当形成凹陷区域时，去除第二间隔物的下部，以在第一和第三间隔物之间​​形成间隙区域。 保护性间隔物填充间隙区域。