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公开(公告)号：US09552171B2
公开(公告)日：2017-01-24
申请号：US14526870
申请日：2014-10-29
Applicant: SanDisk Technologies LLC
Inventor： Yichao Huang , Chris Avila , Dana Lee , Henry Chin , Deepanshu Dutta , Sarath Puthenthermadam , Deepak Raghu
CPC classification number: G06F3/0647 , G06F3/0608 , G06F3/0679 , G06F12/0223 , G06F2212/7205 , G11C16/0483 , G11C16/3431 , G11C16/349 , G11C16/3495 , G11C2211/5644 , G11C2211/5648
Abstract: A number of complimentary techniques for the read scrub process using adaptive counter management are presented. In one set of techniques, in addition to maintaining a cumulative read counter for a block, a boundary word line counter can also be maintained to track the number of reads to most recently written word line or word lines of a partially written block. Another set of techniques used read count threshold values that vary with the number of program/erase cycles that a block has undergone. Further techniques involve setting the read count threshold for a closed (fully written) block based upon the number reads it experienced prior to being closed. These techniques can also be applied at a sub-block, zone level.
Abstract translation: 提出了一些使用自适应计数器管理的读取擦除过程的免费技术。 在一组技术中，除了维持块的累积读计数器之外，还可以维持边界字行计数器以跟踪部分写入块的最近写入的字线或字线的读数。 使用的另一组技术读取计数阈值随着块所经历的编程/擦除周期数而变化。 进一步的技术涉及基于在关闭之前经历的数字读取来设置关闭（完全写入）块的读取计数阈值。 这些技术也可以应用于子区块级别。
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公开(公告)号：US12148489B2
公开(公告)日：2024-11-19
申请号：US17874014
申请日：2022-07-26
Applicant: SanDisk Technologies LLC
Inventor： Yi Song , Sarath Puthenthermadam , Jiahui Yuan
Abstract: An apparatus is provided that includes a block including a word line coupled to a plurality of memory cells, and a control circuit coupled to the word line. The control circuit is configured to program the plurality of memory cells by applying program pulses to the word line in a plurality of program loops, determining a first count of a number of the program loops used to complete programming a first subset of the plurality of memory cells to a first programmed state, first comparing the first count to a corresponding first lower limit and a corresponding first upper limit, and determining whether programming the plurality of memory cells has failed based on a result of the first comparing step.
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公开(公告)号：US20240319905A1
公开(公告)日：2024-09-26
申请号：US18358661
申请日：2023-07-25
Applicant: SanDisk Technologies LLC
Inventor： Longju Liu , Yi Song , Sarath Puthenthermadam , Jiahui Yuan
IPC: G06F3/06
CPC classification number: G06F3/0652 , G06F3/0619 , G06F3/0679
Abstract: A memory system performs an erase process for the non-volatile memory cells including performing erase verify for the non-volatile memory cells. The erase verify comprises comparing threshold voltages of the non-volatile memory cells to an erase verify reference voltage and determining whether an amount of the non-volatile memory cells having a threshold voltage greater than the erase verify reference voltage is less than an allowed bit count. During the erase process, the system compares threshold voltages of the non-volatile memory cells to an intermediate reference voltage that is greater than the erase verify reference voltage and determines an amount of non-volatile memory cells having threshold voltages greater than the intermediate reference voltage. The Allowed Bit Count is increased (during the erase process) by the amount of non-volatile memory cells having threshold voltages greater than the intermediate reference voltage.
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34.发明授权公开(公告)号：US12094537B2
公开(公告)日：2024-09-17
申请号：US17549471
申请日：2021-12-13
Applicant: SanDisk Technologies LLC
Inventor： Yi Song , Dengtao Zhao , Sarath Puthenthermadam , Jiahui Yuan
CPC classification number: G11C16/102 , G11C7/04 , G11C16/24 , G11C16/26 , G11C16/30
Abstract: A system has been described that performs differential temperature compensation based on a differential between the temperature at time of programming and temperature at time of reading for a set of data. Differential temperature compensation is useful for bulk programming/reading (e.g., many pages of data) and/or programming/reading super pages of data (multiple pages residing on different memory die).
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公开(公告)号：US20240038315A1
公开(公告)日：2024-02-01
申请号：US17874014
申请日：2022-07-26
Applicant: SanDisk Technologies LLC
Inventor： Yi Song , Sarath Puthenthermadam , Jiahui Yuan
IPC: G11C29/12 , G11C11/408 , G11C16/08 , G11C16/26 , G11C16/34
CPC classification number: G11C29/12005 , G11C11/4085 , G11C16/08 , G11C16/26 , G11C16/3454 , G11C16/0483
Abstract: An apparatus is provided that includes a block including a word line coupled to a plurality of memory cells, and a control circuit coupled to the word line. The control circuit is configured to program the plurality of memory cells by applying program pulses to the word line in a plurality of program loops, determining a first count of a number of the program loops used to complete programming a first subset of the plurality of memory cells to a first programmed state, first comparing the first count to a corresponding first lower limit and a corresponding first upper limit, and determining whether programming the plurality of memory cells has failed based on a result of the first comparing step.
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Patent Agency Ranking
公开(公告)号：US20230253047A1
公开(公告)日：2023-08-10
申请号：US17665824
申请日：2022-02-07
Applicant: SanDisk Technologies LLC
Inventor： Xue Pitner , Yu-Chung Lien , Sarath Puthenthermadam , Sujjatul Islam
CPC classification number: G11C16/10 , G11C16/0483 , G11C16/24 , G11C16/26 , H01L27/11556
Abstract: A non-volatile semiconductor memory device, described herein, comprises non-volatile storage elements and one or more control circuits in communication with the non-volatile storage elements. The one or more control circuits are configured to, during a program iteration of a program operation, determine whether a program voltage level of the program iteration exceeds a threshold program voltage level and in response to the determination, identify a set of voltage levels to apply to a source line connected to a set of the non-volatile storage elements. The one or more control circuits are further configured to perform the program iteration of the program operation on the set of non-volatile storage elements, where the program iteration includes applying the set of voltage levels to the source line.
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37.发明申请公开(公告)号：US20220180948A1
公开(公告)日：2022-06-09
申请号：US17113920
申请日：2020-12-07
Applicant: SanDisk Technologies LLC
Inventor： Sarath Puthenthermadam , Huai-yuan Tseng
Abstract: A memory apparatus and method of operation is provided. The apparatus includes a block having memory cells connected to word lines and arranged in strings and is divided into a first sub-block and a second sub-block each configured to be erased as a whole in an erase operation. The apparatus has a temperature measuring circuit configured to detect an ambient temperature of the apparatus. A control circuit is configured to determine a word line inhibit voltage based on the ambient temperature. The control circuit applies an erase voltage to each of the strings while simultaneously applying a word line erase voltage to the word lines associated with a selected one of the first and second sub-blocks to encourage erasing and the word line inhibit voltage to the word lines associated with an unselected one of the first and second sub-blocks to discourage erasing in the erase operation.
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公开(公告)号：US10714169B1
公开(公告)日：2020-07-14
申请号：US16437355
申请日：2019-06-11
Applicant: SanDisk Technologies LLC
Inventor： Phil Reusswig , Pitamber Shukla , Sarath Puthenthermadam , Mohan Dunga , Sahil Sharma , Rohit Sehgal , Niles Yang
Abstract: A non-volatile memory system and corresponding method of operation are provided. The system includes non-volatile memory cells, each retaining a threshold voltage within a threshold window. The non-volatile memory cells include multi-bit cells each configured to store a plurality of bits of data with the threshold window partitioned into bands each having a band width. The bands include a lowest band denoting an erased state and increasing bands. A control circuit programs a first set of the data into the multi-bit cells in a single-bit mode using first target states being one of the erased state and a tight intermediate state having a distribution of the threshold voltage no wider than the band width of one of the increasing bands. The control circuit also programs a second set of the data into the multi-bit cells in a multi-bit mode with each of the multi-bit cells storing the plurality of bits.
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公开(公告)号：US20190214100A1
公开(公告)日：2019-07-11
申请号：US15863404
申请日：2018-01-05
Applicant: SanDisk Technologies LLC
Inventor： Sarath Puthenthermadam , Deepanshu Dutta , Long Pham
Abstract: A bad block of memory cells is quickly detected and removed from further programming during concurrent multi-block program operations, to minimize a threshold voltage upshift in a good block. A difference in program speeds between the blocks can be quickly detected by detecting when the memory cells in each block pass a verify test, such as a verify test of a lowest programmed data state. If a first block passes the verify test at a reference program loop, a determination is made as to whether a second block passes the verify test within a specified number of additional program loops. If the second block meets this criterion, the program operation can continue for both blocks. However, if the second block does not meet this criterion, the program operation is terminated for the second block by isolating it from subsequent program and verify signals.
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公开(公告)号：US20180254090A1
公开(公告)日：2018-09-06
申请号：US15816546
申请日：2017-11-17
Applicant: SanDisk Technologies LLC
Inventor： Deepanshu Dutta , Idan Alrod , Huai-Yuan Tseng , Amul Desai , Jun Wan , Ken Cheah , Sarath Puthenthermadam
CPC classification number: G11C16/3413 , G11C8/08 , G11C11/5642 , G11C16/08 , G11C16/16 , G11C16/26 , G11C16/3445 , G11C16/3459 , G11C29/021 , G11C29/028 , G11C2029/1202
Abstract: Techniques are provided for improving the accuracy of read operations of memory cells, where the threshold voltage of the memory cells can shift depending on the coupled up state of the word lines. In one approach, for a read operation, a representative word line voltage in a block is detected and a corresponding set of read voltages is selected. In another approach, a pre-read voltage pulse is applied to a selected word line in response to a read command, just prior to reading the selected cells. In another approach, a voltage pulse is periodically applied to each word line in a block to provide the word lines in a coupled up state. In another approach, a soft erase is performed after a read operation to prevent coupling up of the word lines.
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