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47 条记录 (耗时 0.016 秒)

    Gate drive circuit for reducing reverse recovery current of power device
    33.
    发明授权
    Gate drive circuit for reducing reverse recovery current of power device 有权

    公开(公告)号：US11152936B2

    公开(公告)日：2021-10-19

    申请号：US17044623

    申请日：2020-04-15

    申请人： SOUTHEAST UNIVERSITY

    发明人： Jing Zhu ,  Weifeng Sun ,  Bowei Yang ,  Siyuan Yu ,  Yangyang Lu ,  Longxing Shi

    IPC分类号： H03K3/00 ,  H03K17/08 ,  H03K17/16 ,  H03K17/687 ,  H03K19/20

    摘要： The present invention discloses a gate drive circuit for reducing a reverse recovery current of a power device, and belongs to the field of basic electronic circuit technologies. The gate drive circuit includes a high-voltage LDMOS transistor, a diode forming a freewheeling path when the diode is turned on or a low-voltage MOS transistor in anti-parallel connection with a body diode, and a voltage detection circuit. When the power device is turned off, a freewheeling current produced by an inductive load flows through a freewheeling diode, the voltage detection circuit detects that the freewheeling diode is turned on, and an output signal is processed by a control circuit, to cause the drive circuit to output a high level, so that channels of the power device and the high-voltage LDMOS transistor are turned on, the freewheeling current flows through the conductive channels, almost not through the freewheeling diode, and there is no reverse recovery current in the freewheeling diode at this time, thereby reducing the reverse recovery current of the power device.

    Multiply-accumulate calculation method and circuit suitable for neural network
    34.
    发明授权
    Multiply-accumulate calculation method and circuit suitable for neural network 有权

    公开(公告)号：US10984313B2

    公开(公告)日：2021-04-20

    申请号：US16757421

    申请日：2019-01-24

    申请人： Southeast University

    发明人： Bo Liu ,  Yu Gong ,  Wei Ge ,  Jun Yang ,  Longxing Shi

    IPC分类号： G06N3/063 ,  G06F7/50 ,  G06F7/523 ,  G06F7/544 ,  G06N3/08

    摘要： The present invention relates to the field of analog integrated circuits, and provides a multiply-accumulate calculation method and circuit suitable for a neural network, which realizes large-scale multiply-accumulate calculation of the neural network with low power consumption and high speed. The multiply-accumulate calculation circuit comprises a multiplication calculation circuit array and an accumulation calculation circuit. The multiplication calculation circuit array is composed of M groups of multiplication calculation circuits. Each group of multiplication calculation circuits is composed of one multiplication array unit and eight selection-shift units. The order of the multiplication array unit is quantized in real time by using on-chip training to provide a shared input for the selection-shift units, achieving increased operating rate and reduced power consumption. The accumulation calculation circuit is composed of a delay accumulation circuit, a TDC conversion circuit, and a shift-addition circuit in series. The delay accumulation circuit comprises eight controllable delay chains for dynamically controlling the number of iterations and accumulating data multiple times in a time domain, so as to meet the difference in calculation scale of different network layers, save hardware storage space, reduce calculation complexity, and reduce data scheduling.

    Process corner detection circuit based on self-timing oscillation ring
    35.
    发明授权
    Process corner detection circuit based on self-timing oscillation ring 有权

    公开(公告)号：US10422830B2

    公开(公告)日：2019-09-24

    申请号：US15321111

    申请日：2014-12-26

    申请人： Southeast University

    发明人： Weiwei Shan ,  Longxing Shi ,  Jun Yang

    IPC分类号： G01R31/28 ,  H03K3/03

    摘要： A process corner detection circuit based on a self-timing ring oscillator comprises a reset circuit (1), the self-timing oscillation ring (2), and a counting module (3). The self-timing ring oscillator (2) consists of m two-input Muller C-elements and inverters, and a two-input AND gate, m being a positive integer greater than or equal to 3. The circuit can be used for detecting a process corner of a fabricated integrated circuit chip, and reflecting the process corner of the chip according to the number of oscillations of the self-timing ring oscillator (2). The number of oscillations of the self-timing ring oscillator (2) in different process corners is acquired by Hspice simulation before the chip tape-out, and the process corner of the chip after the chip tape-out can be determined according to the actually measured number of oscillations.

    Online monitoring unit and control circuit for ultra-wide voltage range applications
    36.
    发明授权
    Online monitoring unit and control circuit for ultra-wide voltage range applications 有权

    公开(公告)号：US10268790B2

    公开(公告)日：2019-04-23

    申请号：US15560161

    申请日：2017-02-24

    申请人： Southeast University

    发明人： Weiwei Shan ,  Wentao Dai ,  Jun Yang ,  Longxing Shi

    IPC分类号： G06F17/50 ,  H03K5/19 ,  H03K5/1534

    摘要： An online monitoring unit and a control circuit for ultra-wide voltage range applications are disclosed. Compared with a conventional online monitoring unit, present invention eliminates a need to reserve delay units, replaces flip-flops in the conventional online monitoring unit with a latch, and uses a transition detector with fewer transistors than that of a shadow latch in the conventional online monitoring unit, thereby reducing an area and a power consumption of the online monitoring unit significantly and improving an energy efficiency of online monitoring techniques. In addition, in the ultra-wide voltage range applications, a time borrowing property of the latch adopted by the present invention can be utilized to prevent a timing error caused by process-voltage-temperature (PVT) variations, thus enabling a minimization of a timing margin and ensuring a higher power efficiency. The present invention also discloses a control circuit for use with the online monitoring unit.

    CACHE STRUCTURE AND MANAGEMENT METHOD FOR USE IN IMPLEMENTING RECONFIGURABLE SYSTEM CONFIGURATION INFORMATION STORAGE
    38.
    发明申请
    CACHE STRUCTURE AND MANAGEMENT METHOD FOR USE IN IMPLEMENTING RECONFIGURABLE SYSTEM CONFIGURATION INFORMATION STORAGE 有权
    用于实施可重构系统配置信息存储的缓存结构和管理方法

    公开(公告)号：US20150254180A1

    公开(公告)日：2015-09-10

    申请号：US14425456

    申请日：2013-11-13

    申请人： Southeast University

    发明人： Longxing Shi ,  Jun Yang ,  Peng Cao ,  Bo Liu ,  Jinjiang Yang ,  Leibo Liu ,  Shouyi Yin ,  Shaojun Wei

    IPC分类号： G06F12/06 ,  G06F12/08

    CPC分类号： G06F12/0646 ,  G06F12/0811 ,  G06F12/0895 ,  G06F17/5054 ,  G06F2212/283 ,  G06F2212/601

    摘要： Disclosed is a cache structure for use in implementing reconfigurable system configuration information storage, comprising: layered configuration information cache units: for use in caching configuration information that may be used by a certain or several reconfigurable arrays within a period of time; an off-chip memory interface module: for use in establishing communication; a configuration anagement unit: for use in managing a reconfiguration process of the reconfigurable arrays, in mapping each subtask in an algorithm application to a certain reconfigurable array, thus the reconfigurable array will, on the basis of the mapped subtask, load the corresponding configuration information to complete a function reconfiguration for the reconfigurable array. This increases the utilization efficiency of configuration information caches. Also provided is a method for managing the reconfigurable system configuration information caches, employing a mixed priority cache update method, and changing a mode for managing the configuration information caches in a conventional reconfigurable system, thus increasing the dynamic reconfiguration efficiency in a complex reconfigurable system.

    摘要翻译： 公开了一种用于实现可重构系统配置信息存储的缓存结构，包括：分层配置信息高速缓存单元：用于缓存在一段时间内由特定或多个可重配置阵列使用的配置信息; 片外存储器接口模块：用于建立通信; 配置管理单元：用于管理可重新配置阵列的重新配置过程，将算法应用中的每个子任务映射到某个可重配置阵列，因此可重构阵列将基于映射子任务加载相应的配置信息 完成可重构阵列的功能重新配置。 这增加了配置信息高速缓存的使用效率。 还提供了一种用于管理可重配置系统配置信息高速缓存的方法，采用混合优先级高速缓存更新方法，以及改变用于管理常规可重新配置系统中的配置信息高速缓存的模式，从而增加复杂可重新配置系统中的动态重新配置效率。

    CIRCUIT FOR ENHANCING ROBUSTNESS OF SUB-THRESHOLD SRAM MEMORY CELL
    39.
    发明申请
    CIRCUIT FOR ENHANCING ROBUSTNESS OF SUB-THRESHOLD SRAM MEMORY CELL 有权
    用于增强次级SRAM存储器单元的稳定性的电路

    公开(公告)号：US20140376305A1

    公开(公告)日：2014-12-25

    申请号：US14369651

    申请日：2012-12-27

    申请人： SOUTHEAST UNIVERSITY

    发明人： Na Bai ,  Longxing Shi ,  Jun Yang ,  Xinning Liu ,  Jiafeng Zhu ,  Yue Feng ,  Cai Gong ,  Fei Pan ,  Hong Chang ,  Yifeng Deng ,  Yuan Chen ,  Yingcheng Xia

    IPC分类号： G11C11/419 ,  H01L27/11

    CPC分类号： G11C11/419 ,  G11C11/412 ,  G11C11/417 ,  H01L27/1104

    摘要： The present invention discloses a circuit for improving process robustness of sub-threshold SRAM memory cells, which serves as an auxiliary circuit for a sub-threshold SRAM memory cell. The output of the circuit is connected to the PMOS tube of the sub-threshold SRAM memory cell and the substrate of a PMOS tube in the circuit. The circuit comprises a detection circuit for threshold voltage of PMOS tube and a differential input and single-ended output amplifier. The circuit changes the substrate voltage of the PMOS tubes in the sub-threshold SRAM memory cell and the substrate voltage of the PMOS tube in the circuit in a self-adapting manner by detecting threshold voltage fluctuations of PMOS tubes and NMOS tubes resulted from process fluctuations and thereby regulate the threshold voltages of the PMOS tubes, so that the threshold voltage of PMOS tubes matches the threshold voltage of NMOS tubes. The circuit improves the noise margin of sub-threshold SRAM memory cells and effectively improves the process robustness of sub-threshold SRAM memory cells.

    摘要翻译： 本发明公开了一种用于提高亚阈值SRAM存储单元的处理鲁棒性的电路，其用作子阈值SRAM存储单元的辅助电路。 电路的输出连接到子阈值SRAM存储单元的PMOS管和电路中的PMOS管的衬底。 该电路包括用于PMOS管的阈值电压的检测电路和差分输入和单端输出放大器。 该电路通过检测来自过程波动的PMOS管和NMOS管的阈值电压波动，以自适应方式改变子阈值SRAM存储单元中的PMOS管的衬底电压和电路中的PMOS管的衬底电压 从而调节PMOS管的阈值电压，使得PMOS管的阈值电压与NMOS管的阈值电压相匹配。 该电路提高了亚阈值SRAM存储单元的噪声容限，有效提高了亚阈值SRAM存储单元的工艺稳健性。

    HIGH-CURRENT N-TYPE SILICON-ON-INSULATOR LATERAL INSULATED-GATE BIPOLAR TRANSISTOR
    40.
    发明申请
    HIGH-CURRENT N-TYPE SILICON-ON-INSULATOR LATERAL INSULATED-GATE BIPOLAR TRANSISTOR 有权
    高电流N型绝缘子硅酸盐绝缘栅双极晶体管

    公开(公告)号：US20140306266A1

    公开(公告)日：2014-10-16

    申请号：US14349632

    申请日：2012-10-24

    申请人： SOUTHEAST UNIVERSITY

    发明人： Weifeng Sun ,  Siyang Liu ,  Jing Zhu ,  Qinsong Qian ,  Shen Xu ,  Shengli Lu ,  Longxing Shi

    IPC分类号： H01L29/739 ,  H01L27/12 ,  H01L27/06

    CPC分类号： H01L29/7394 ,  H01L27/0623 ,  H01L27/1203 ,  H01L29/0638 ,  H01L29/404

    摘要： A high-current, N-type silicon-on-insulator lateral insulated-gate bipolar transistor, including: a P-type substrate, a buried-oxide layer disposed on the P-type substrate, an N-type epitaxial layer disposed on the oxide layer, and an N-type buffer trap region. A P-type body region and an N-type central buffer trap region are disposed inside the N-type epitaxial layer; a P-type drain region is disposed in the buffer trap region; N-type source regions and a P-type body contact region are disposed in the P-type body region; an N-type base region and a P-type emitter region are disposed in the buffer trap region; gate and field oxide layers are disposed on the N-type epitaxial layer; polycrystalline silicon gates are disposed on the gate oxide layers; and a passivation layer and metal layers are disposed on the surface of the symmetrical transistor. P-type emitter region output and current density are improved without increasing the area of the transistor.

    摘要翻译： 一种高电流，N型绝缘体上的横向绝缘栅双极晶体管，包括：P型衬底，设置在P型衬底上的掩埋氧化物层，设置在P型衬底上的N型外延层 氧化物层和N型缓冲阱捕获区。 P型体区域和N型中央缓冲区捕获区域设置在N型外延层内部; P型漏极区域设置在缓冲陷阱区域中; N型源极区域和P型体接触区域设置在P型体区域中; N型基极区域和P型发射极区域设置在缓冲陷阱区域中; 栅极和场氧化物层设置在N型外延层上; 多晶硅栅极设置在栅极氧化物层上; 并且钝化层和金属层设置在对称晶体管的表面上。 改善P型发射极区域的输出和电流密度，而不增加晶体管的面积。