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    LATCH-TYPE SENSE AMPLIFIER FOR A NON-VOLATILE MEMORY WITH REDUCED MARGIN BETWEEN SUPPLY VOLTAGE AND BITLINE-SELECTION VOLTAGE
    31.
    发明申请
    LATCH-TYPE SENSE AMPLIFIER FOR A NON-VOLATILE MEMORY WITH REDUCED MARGIN BETWEEN SUPPLY VOLTAGE AND BITLINE-SELECTION VOLTAGE 有权

    公开(公告)号：US20210020237A1

    公开(公告)日：2021-01-21

    申请号：US16931335

    申请日：2020-07-16

    申请人： STMicroelectronics S.r.l.

    发明人： Marcella Carissimi ,  Laura Capecchi ,  Marco Pasotti ,  Fabio Enrico Carlo Disegni

    IPC分类号： G11C13/00

    摘要： A sense amplifier and a method for accessing a memory device are disclosed. In an embodiment a sense amplifier for a memory device includes a first input node selectively coupled to a first memory cell through a first local bitline and a first main bitline, a second input node selectively coupled through a second local bitline and a second main bitline to a second memory cell or to a reference generator configured to generate a reference current, a first current generator controllable so as to inject a first variable current into the first input node, a second current generator controllable so as to inject a second variable current into the second input node, a first branch coupled to the first input node and comprising a first switch circuit, a first sense transistor and a first forcing transistor and a second branch coupled to the second input node and including a second switch circuit, a second sense transistor and a second forcing transistor.

    NONVOLATILE, ELECTRICALLY NON-PROGRAMMABLE MEMORY DEVICE AND MANUFACTORY PROCESS THEREOF
    32.
    发明申请
    NONVOLATILE, ELECTRICALLY NON-PROGRAMMABLE MEMORY DEVICE AND MANUFACTORY PROCESS THEREOF 审中-公开

    公开(公告)号：US20190130970A1

    公开(公告)日：2019-05-02

    申请号：US16169763

    申请日：2018-10-24

    申请人： STMicroelectronics S.r.l.

    发明人： Marcella Carissimi ,  Marco Pasotti ,  Chantal Auricchio

    IPC分类号： G11C13/00

    摘要： The ROM device has a memory array including memory cells formed by an access element and a data storage element; a high voltage column decoder stage; a high voltage row decoder stage; an analog stage; and a writing stage, wherein the data storage elements are electrically non-programmable and non-modifiable. The memory array is formed by memory cells having a first logic state and by memory cells having a second logic state. The data storage element of the memory cells having the first logic state is formed by a continuous conductive path uninterruptedly connecting the access transistor to the respective bit line, the data storage element of the memory cells having the second logic state is formed by a region of dielectric material insulating the access transistor from the respective bit line.

    IDENTIFICATION OF A CONDITION OF A SECTOR OF MEMORY CELLS IN A NON-VOLATILE MEMORY
    33.
    发明申请
    IDENTIFICATION OF A CONDITION OF A SECTOR OF MEMORY CELLS IN A NON-VOLATILE MEMORY 审中-公开

    公开(公告)号：US20170200483A1

    公开(公告)日：2017-07-13

    申请号：US15471028

    申请日：2017-03-28

    申请人： STMicroelectronics S.r.l.

    发明人： Marcella Carissimi ,  Marco Pasotti ,  Fabio De Santis

    IPC分类号： G11C7/22 ,  G11C7/06

    CPC分类号： G11C7/22 ,  G11C7/06 ,  G11C7/062 ,  G11C7/08 ,  G11C7/10 ,  G11C16/0441 ,  G11C16/28

    摘要： A non-volatile memory of a complementary type includes sectors of memory cells, with each cell formed by a direct memory cell and a complementary memory cell. Each sector is in a non-written condition when the corresponding memory cells are in equal states and is in a written condition wherein each location thereof stores a first logic value or a second logic value when the memory cells of the location are in a first combination of different states or in a second combination of different states, respectively. A sector is selected and a determination is made as to a number of memory cells in the programmed state and a number of memory cells in the erased state. From this information, the condition of the selected sector is identified from a comparison between the number of memory cells in the programmed state and the number of memory cells in the erased state.

    IDENTIFICATION OF A CONDITION OF A SECTOR OF MEMORY CELLS IN A NON-VOLATILE MEMORY
    35.
    发明申请
    IDENTIFICATION OF A CONDITION OF A SECTOR OF MEMORY CELLS IN A NON-VOLATILE MEMORY 有权
    识别非易失性存储器中存储器细胞的一个条件的条件

    公开(公告)号：US20160064046A1

    公开(公告)日：2016-03-03

    申请号：US14938304

    申请日：2015-11-11

    申请人： STMICROELECTRONICS S.R.L.

    发明人： Marcella Carissimi ,  Marco Pasotti ,  Fabio De Santis

    IPC分类号： G11C7/06

    CPC分类号： G11C7/22 ,  G11C7/06 ,  G11C7/062 ,  G11C7/08 ,  G11C7/10 ,  G11C16/0441 ,  G11C16/28

    摘要： A non-volatile memory of a complementary type includes sectors of memory cells, with each cell formed by a direct memory cell and a complementary memory cell. Each sector of the non-volatile memory is in a non-written condition when the corresponding memory cells are in equal states and is in a written condition wherein each location thereof stores a first logic value or a second logic value when the memory cells of the location are in a first combination of different states or in a second combination of different states, respectively. A sector is selected and a determination is made as to a number of memory cells in the programmed state and a number of memory cells in the erased state. From this information, the condition of the selected sector is identified from a comparison between the number of memory cells in the programmed state and the number of memory cells in the erased state.

    摘要翻译： 互补型的非易失性存储器包括存储器单元的扇区，每个单元由直接存储单元和互补存储单元形成。 当相应的存储器单元处于相同的状态并且处于写入状态时，非易失性存储器的每个扇区处于非写入状态，其中当其中的每个位置存储第一逻辑值或第二逻辑值时， 位置分别处于不同状态的第一组合或处于不同状态的第二组合中。 选择扇区，并且确定处于编程状态的多个存储单元和被擦除状态的多个存储单元。 根据该信息，通过编程状态下的存储单元的数量和被擦除状态的存储单元的数量之间的比较来识别所选扇区的状态。

    Memory device and method for in-memory computing
    36.
    发明授权
    Memory device and method for in-memory computing 有权

    公开(公告)号：US11756615B2

    公开(公告)日：2023-09-12

    申请号：US17462250

    申请日：2021-08-31

    申请人： STMicroelectronics S.r.l.

    发明人： Marcella Carissimi ,  Marco Pasotti ,  Roberto Antonio Canegallo

    IPC分类号： G11C11/00 ,  G11C13/00 ,  G06N3/02

    CPC分类号： G11C13/0026 ,  G11C13/003 ,  G11C13/004 ,  G11C13/0004 ,  G11C13/0038 ,  G06N3/02

    摘要： An embodiment memory device comprises a plurality of memory cells, each exhibiting a transconductance depending on a value of a stored bit, a plurality of bit lines associated with respective groups of memory cells, each bit line configured to flow a respective electric current indicative of the bit stored in a selected memory cell of the respective group of memory cells, and a computing circuit providing an output electric quantity indicative of a linear combination of a plurality of input electric quantities. The computing circuit comprises a biasing stage configured to bias each bit line with a respective input electric quantity, the electric current flowing through each bit line based on a product of the respective input electric quantity and the transconductance of the selected memory cell, and a combining stage for combining the electric currents flowing through the plurality of bit lines thereby obtaining the output electric quantity.

    MEMORY DEVICE AND METHOD FOR IN-MEMORY COMPUTING
    37.
    发明申请
    MEMORY DEVICE AND METHOD FOR IN-MEMORY COMPUTING 有权

    公开(公告)号：US20220068380A1

    公开(公告)日：2022-03-03

    申请号：US17462250

    申请日：2021-08-31

    申请人： STMicroelectronics S.r.l.

    发明人： Marcella Carissimi ,  Marco Pasotti ,  Roberto Canegallo

    IPC分类号： G11C13/00

    摘要： An embodiment memory device comprises a plurality of memory cells, each exhibiting a transconductance depending on a value of a stored bit, a plurality of bit lines associated with respective groups of memory cells, each bit line configured to flow a respective electric current indicative of the bit stored in a selected memory cell of the respective group of memory cells, and a computing circuit providing an output electric quantity indicative of a linear combination of a plurality of input electric quantities. The computing circuit comprises a biasing stage configured to bias each bit line with a respective input electric quantity, the electric current flowing through each bit line based on a product of the respective input electric quantity and the transconductance of the selected memory cell, and a combining stage for combining the electric currents flowing through the plurality of bit lines thereby obtaining the output electric quantity.