公开(公告)号：US20100044704A1

公开(公告)日：2010-02-25

申请号：US12544548

申请日：2009-08-20

申请人： Barry John Male ,  Philip L. Hower

发明人： Barry John Male ,  Philip L. Hower

IPC分类号： H01L29/66 ,  H01L21/70

CPC分类号： H01L35/30 ,  H01L23/38 ,  H01L27/16 ,  H01L35/22 ,  H01L35/32 ,  H01L2924/0002 ,  H01L2924/3011 ,  H01L2924/00

摘要： A thermoelectric device is disclosed which includes metal thermal terminals protruding from a top surface of an IC, connected to vertical thermally conductive conduits made of interconnect elements of the IC. Lateral thermoelectric elements are connected to the vertical conduits at one end and heatsinked to the IC substrate at the other end. The lateral thermoelectric elements are thermally isolated by interconnect dielectric materials on the top side and field oxide on the bottom side. When operated in a generator mode, the metal thermal terminals are connected to a heat source and the IC substrate is connected to a heat sink. Thermal power flows through the vertical conduits to the lateral thermoelectric elements, which generate an electrical potential. The electrical potential may be applied to a component or circuit in the IC. The thermoelectric device may be integrated into an IC without adding fabrication cost or complexity.

摘要翻译： 公开了一种热电装置，其包括从IC的顶表面突出的金属热端子，其连接到由IC的互连元件制成的垂直导热导管。 侧向热电元件在一端连接到垂直导管，并在另一端与IC基板相互散热。 侧向热电元件通过顶侧的互连电介质材料和底侧的场氧化物热隔离。 当在发电机模式下工作时，金属热端子连接到热源，并且IC基板连接到散热器。 热功率流过垂直管道到横向热电元件，产生电位。 电位可以施加到IC中的元件或电路。 热电装置可以集成到IC中而不增加制造成本或复杂性。

公开(公告)号：US08476127B2

公开(公告)日：2013-07-02

申请号：US13284011

申请日：2011-10-28

申请人： Marie Denison ,  Sameer Pendharkar ,  Philip L. Hower

发明人： Marie Denison ,  Sameer Pendharkar ,  Philip L. Hower

IPC分类号： H01L21/336

CPC分类号： H01L29/7816 ,  H01L21/265 ,  H01L21/823814 ,  H01L27/0922 ,  H01L29/0696 ,  H01L29/0847 ,  H01L29/0878 ,  H01L29/1083 ,  H01L29/66659 ,  H01L29/66681 ,  H01L29/7835

摘要： An integrated circuit containing a dual drift layer extended drain MOS transistor with an upper drift layer contacting a lower drift layer along at least 75 percent of a common length of the two drift layers. An average doping density in the lower drift layer is between 2 and 10 times an average doping density in the upper drift layer. A process of forming an integrated circuit containing a dual drift layer extended drain MOS transistor with a lower drift extension under the body region and an isolation link which electrically isolates the body region, using an epitaxial process. A process of forming an integrated circuit containing a dual drift layer extended drain MOS transistor with a lower drift extension under the body region and an isolation link which electrically isolates the body region, on a monolithic substrate.

摘要翻译： 一种包含双漂移层延伸漏极MOS晶体管的集成电路，其上部漂移层沿着两个漂移层的公共长度的至少75％与下部漂移层接触。 下漂移层中的平均掺杂密度在上漂移层中的平均掺杂密度的2至10倍。 一种形成集成电路的过程，该集成电路包含在体区内具有较低漂移延伸的双漂移层延伸漏极MOS晶体管，以及使用外延工艺电隔离体区的隔离链路。 一种形成集成电路的过程，该集成电路包含在主体区域具有较低漂移延伸的双漂移层延伸漏极MOS晶体管和在整体式衬底上电隔离体区的隔离链路。

公开(公告)号：US08461589B1

公开(公告)日：2013-06-11

申请号：US13489257

申请日：2012-06-05

申请人： Philip L. Hower ,  Barry Jon Male ,  Wilburn M. Miller

发明人： Philip L. Hower ,  Barry Jon Male ,  Wilburn M. Miller

IPC分类号： H01L23/36 ,  H01L23/58 ,  H01L23/34

CPC分类号： H01L23/345 ,  H01L22/14 ,  H01L23/3677 ,  H01L23/5228 ,  H01L2924/0002 ,  H01L2924/00

摘要： An integrated circuit (IC) includes a heated portion. The heated portion/IC includes a substrate having a topside semiconductor surface having circuitry configured to provide a circuit function. A pre-metal dielectric (PMD) layer is on the topside semiconductor surface. A metal interconnect stack is on the PMD. A trim portion includes one or more temperature sensitive circuit components which affect a temperature behavior of the IC. The heated portion extends over and beyond an area of the trim portion having an integrated heating structure including at least a first heater formed from a metal interconnect level that includes a first plurality of winding segments which have a varying pitch. A heat spreader formed from a second metal interconnect layer is between trim portion and the first heater. Thermal plugs are lateral to the temperature sensitive circuit components and thermally couple the heat spreader to the topside semiconductor surface.

摘要翻译： 集成电路（IC）包括加热部分。 加热部分/ IC包括具有顶侧半导体表面的基板，其具有被配置为提供电路功能的电路。 前金属电介质（PMD）层位于顶侧半导体表面上。 PMD上有一个金属互连堆叠。 修整部分包括影响IC的温度特性的一个或多个温度敏感电路部件。 加热部分延伸超过具有整体加热结构的修整部分的区域，该整体加热结构至少包括由金属互连级别形成的第一加热器，该第一加热器包括具有变化间距的第一多个绕组段。 由第二金属互连层形成的散热器在修剪部分和第一加热器之间。 热插头是温度敏感电路部件的侧面，并将散热器热耦合到顶侧半导体表面。

公开(公告)号：US07989853B2

公开(公告)日：2011-08-02

申请号：US12537589

申请日：2009-08-07

申请人： Pinghai Hao ,  Sameer Pendharkar ,  Philip L. Hower ,  Marie Denison

发明人： Pinghai Hao ,  Sameer Pendharkar ,  Philip L. Hower ,  Marie Denison

IPC分类号： H01L29/66 ,  H01L21/337

CPC分类号： H01L27/098 ,  H01L29/0649 ,  H01L29/1058 ,  H01L29/402 ,  H01L29/808

摘要： A dual channel JFET which can be integrated in an IC without adding process steps is disclosed. Pinch-off voltage is determined by lateral width of a first, vertical, channel near the source contact. Maximum drain voltage is determined by drain to gate separation and length of a second, horizontal, channel under the gate. Pinch-off voltage and maximum drain potential are dependent on lateral dimensions of the drain and gate wells and may be independently optimized. A method of fabricating the dual channel JFET is also disclosed.

摘要翻译： 公开了可以集成在IC中而不添加工艺步骤的双通道JFET。 夹断电压由源触点附近的第一垂直通道的横向宽度决定。 最大漏极电压由漏极到栅极间隔和栅极下方的第二个水平沟道的长度决定。 夹断电压和最大漏极电位取决于漏极和栅极阱的横向尺寸，并且可以独立优化。 还公开了制造双通道JFET的方法。

公开(公告)号：US06958515B2

公开(公告)日：2005-10-25

申请号：US10036323

申请日：2001-12-31

申请人： Philip L. Hower ,  Taylor R. Efland

发明人： Philip L. Hower ,  Taylor R. Efland

IPC分类号： H01L27/085 ,  H01L21/336 ,  H01L29/08 ,  H01L29/10 ,  H01L29/417 ,  H01L29/423 ,  H01L29/45 ,  H01L29/78 ,  H01L29/76

CPC分类号： H01L29/7816 ,  H01L29/0878 ,  H01L29/1095 ,  H01L29/41766 ,  H01L29/42368 ,  H01L29/456 ,  H01L29/66689

摘要： An improved n-channel integrated lateral DMOS (10) in which a buried body region (30), beneath and self-aligned to the source (18) and normal body diffusions, provides a low impedance path for holes emitted at the drain region (16). This greatly reduces secondary electron generation, and accordingly reduces the gain of the parasitic PNP bipolar device. The reduced regeneration in turn raises the critical field value, and hence the safe operating area.

摘要翻译： 改进的n沟道集成横向DMOS（10），其中在源极（18）下方并自对准并且正常体扩散的掩埋体区域（30）为漏极区域处发射的空穴提供低阻抗路径（ 16）。 这大大减少了二次电子产生，从而降低了寄生PNP双极器件的增益。 减少的再生反过来提高了临界场值，从而提高了安全操作面积。

公开(公告)号：US5164813A

公开(公告)日：1992-11-17

申请号：US700107

申请日：1991-05-08

申请人： Scott C. Blackstone ,  Philip L. Hower ,  Elizabeth M. Roughan ,  Christopher H. Doucette ,  Roy Lee ,  Carolyn Q. Cotnam

发明人： Scott C. Blackstone ,  Philip L. Hower ,  Elizabeth M. Roughan ,  Christopher H. Doucette ,  Roy Lee ,  Carolyn Q. Cotnam

IPC分类号： H01L21/18 ,  H01L21/329 ,  H01L23/051 ,  H01L29/861

CPC分类号： H01L29/66113 ,  H01L21/187 ,  H01L23/051 ,  H01L24/01 ,  H01L29/861 ,  H01L29/8613 ,  H01L2924/12035 ,  H01L2924/12036 ,  H01L2924/12042 ,  H01L2924/12043

摘要： A new diode structure is provided by bonding two semiconductor materials together having a low capacitance, a large contact area and mechanical ruggedness. The cross-sectional area of at least one of the semiconductor materials is reduced in the region of the bond resulting in a structure with either an hourglass or truncated hourglass-like cross-section. A diode PN junction is contained in the neighborhood of the area of reduced cross section. The diode so constructed provides a sufficient spacing between the unbonded semiconductor regions to reduce total packaged diode capacitance without introducing a spacer layer. The diode is processed to limit the area of the PN junction formed therein to the region of the bonding between the semiconductor materials, without limiting the metallized contact area, further controlling the diode capacitance as well as other electrical characteristics. The outer ends of the diode parallel to the bond, comprising typically P and N type semiconductor regions, are typically connected to metal leads which comprise the diode leads and the diode is packaged to form a mechanically and electrically stable low capacitance diode. This diode can be encapsulated such that no void or cavity exists within the interior of the structure without changing the diode construction process.

摘要翻译： 通过将两个半导体材料结合在一起，具有低电容，大的接触面积和机械坚固性来提供新的二极管结构。 至少一种半导体材料的横截面面积在结合区域中减小，从而产生具有沙漏或截短的沙漏状横截面的结构。 二极管PN结包含在减小截面的区域附近。 如此构造的二极管在未连接的半导体区域之间提供足够的间隔，以减少总封装的二极管电容而不引入间隔层。 处理二极管以限制形成在其中的PN结的区域到半导体材料之间的接合区域，而不限制金属化接触面积，进一步控制二极管电容以及其它电特性。 平行于键合的二极管的外端，通常包括P型和N型半导体区，通常连接到包括二极管引线的金属引线，并且二极管被封装以形成机械和电气稳定的低电容二极管。 该二极管可以被封装成使得在结构内部不存在空隙或空腔而不改变二极管构造过程。

公开(公告)号：US4901120A

公开(公告)日：1990-02-13

申请号：US61189

申请日：1987-06-10

申请人： Carson E. Weaver ,  Philip L. Hower

发明人： Carson E. Weaver ,  Philip L. Hower

IPC分类号： H01L29/73 ,  H01L29/861 ,  H01L29/872

CPC分类号： H01L29/8611 ,  H01L29/7302 ,  H01L29/872

摘要： A bipolar junction structure comprising a Schottky barrier rectifying contact juxtaposed to a p-n junction having the distribution of p+ diffusions common to a guard ring structure on the Schottky barrier area.

摘要翻译： 一种双极结结构，包括与肖特基势垒区上的保护环结构共有的p +扩散分布的p-n结并置的肖特基势垒整流触点。

公开(公告)号：US4551353A

公开(公告)日：1985-11-05

申请号：US633675

申请日：1984-07-24

申请人： Philip L. Hower ,  Eric K. Li

发明人： Philip L. Hower ,  Eric K. Li

IPC分类号： H01L21/3105 ,  H01L21/56 ,  H01L21/326

CPC分类号： H01L21/3105 ,  H01L21/56 ,  H01L23/3178 ,  H01L2224/16225 ,  H01L2924/13033 ,  H01L2924/13034 ,  Y10S438/91 ,  Y10S438/958

摘要： A method for reducing leakage currents in passivated semiconductor devices includes subjecting the passivation layer to a corona discharge for reducing or eliminating the inversion layer produced by the characteristic passivation layer charge.

摘要翻译： 一种用于减少钝化半导体器件中漏电流的方法包括使钝化层进行电晕放电以减少或消除由特征钝化层电荷产生的反型层。

公开(公告)号：US4231059A

公开(公告)日：1980-10-28

申请号：US956813

申请日：1978-11-01

申请人： Philip L. Hower ,  Derrick J. Page

发明人： Philip L. Hower ,  Derrick J. Page

IPC分类号： H01L29/41 ,  H01L21/331 ,  H01L23/48 ,  H01L23/482 ,  H01L29/417 ,  H01L29/73 ,  H01L29/74

CPC分类号： H01L23/4824 ,  H01L24/72 ,  H01L29/41708 ,  H01L2924/01005 ,  H01L2924/01006 ,  H01L2924/01013 ,  H01L2924/01015 ,  H01L2924/01019 ,  H01L2924/01023 ,  H01L2924/01033 ,  H01L2924/01042 ,  H01L2924/01047 ,  H01L2924/01051 ,  H01L2924/01057 ,  H01L2924/01074 ,  H01L2924/01075 ,  H01L2924/01079 ,  H01L2924/01082 ,  H01L2924/12033 ,  H01L2924/12036 ,  H01L2924/1301 ,  H01L2924/19043

摘要： A transistor in which this effective emitter resistance which is determined by the geometry of the emitter metallization as disclosed. In the preferred embodiment, the emitter metallization comprises a series of circular "dots" which are distributed over the entire emitter area. The area of the "dots" with respect to the entire emitter area is selected such that the desired effective emitter resistance is achieved.

摘要翻译： 其中这种有效发射极电阻由发射体金属化的几何形状确定的晶体管，如所公开的。 在优选实施例中，发射极金属化包括分布在整个发射极区域上的一系列圆形“点”。 选择相对于整个发射极区域的“点”的面积，使得实现期望的有效发射极电阻。

公开(公告)号：US4112362A

公开(公告)日：1978-09-05

申请号：US755619

申请日：1976-12-30

申请人： Philip L. Hower ,  William G. Carlson ,  Tapan K. Gupta

发明人： Philip L. Hower ,  William G. Carlson ,  Tapan K. Gupta

IPC分类号： G01R31/12 ,  G01R15/00 ,  G01R31/00 ,  G01R31/16 ,  G01R31/02

CPC分类号： G01R31/00 ,  G01R15/00

摘要： A method for the nondestructive testing of voltage limiting blocks includes the steps of providing several discrete electrical contacts across the block, sequentially applying to each of the contacts a voltage to determine the corresponding current and utilizing the current and voltage values to determine constants related to the microstructure of that particular location. The constants can then be utilized to derive a contour map which will be indicative of a hot spot in such block as determined by a maxima of the contour map.

摘要翻译： 用于电压限制块的非破坏性测试的方法包括以下步骤：在块上提供几个离散的电触点，顺序地向每个触点施加电压以确定相应的电流并利用电流和电压值来确定与 该特定位置的微观结构。 然后可以使用常数来导出轮廓图，其将指示由等高线图的最大值确定的这种块中的热点。