公开(公告)号：US11626165B2

公开(公告)日：2023-04-11

申请号：US17888743

申请日：2022-08-16

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Yohan Lee ,  Sangwan Nam ,  Sangwon Park

IPC: G11C16/10 ,  G11C16/16 ,  G11C16/26 ,  G11C16/04 ,  G11C16/32 ,  G11C16/08 ,  G11C16/30

Abstract: A memory device includes a cell area including memory blocks, and a peripheral circuit area including peripheral circuits that execute an erase operation for each of the memory blocks. Each memory block includes word lines that are stacked on a substrate, channel structures penetrate through the word lines, and a source region that is disposed on the substrate and connected to the channel structures. During the erase operation in which an erase voltage is provided to the source region of a target memory block among the memory blocks, the peripheral circuits reduce a voltage of a first word line from a first bias voltage to a second bias voltage at a first time, and to reduce a voltage of a second word line, different from the first word line, from a third bias voltage to a fourth bias voltage at a second time different from the first time.

公开(公告)号：US20230096057A1

公开(公告)日：2023-03-30

申请号：US17817408

申请日：2022-08-04

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Hanjun Lee ,  Byungsoo Kim ,  Sangwan Nam

IPC: G11C16/10 ,  G11C16/04 ,  G11C16/34

Abstract: A program method includes applying a first voltage to a plurality of bit lines, applying a second voltage to a common source line (CSL), and performing a program loop by applying a program voltage and a verify voltage to each of a plurality of ground selection lines (GSLs) positioned between one bit line among the plurality of bit lines and the CSL. The program loop is performed on both a program completed cell in which a program is completed by applying the program voltage and a program target cell.

公开(公告)号：US11615855B2

公开(公告)日：2023-03-28

申请号：US17334045

申请日：2021-05-28

Applicant: Samsung Electronics Co., Ltd.

Inventor： Yonghyuk Choi ,  Sangwan Nam ,  Jaeduk Yu ,  Yohan Lee

IPC: G11C16/04 ,  G11C16/34 ,  G11C16/08 ,  G11C16/10 ,  G11C16/24 ,  H01L23/00 ,  H01L25/065 ,  H01L25/18 ,  H01L27/11556 ,  H01L27/11582

Abstract: A nonvolatile memory device includes at least one memory block and a control circuit. The at least one memory block includes a plurality of cell strings, each including a string selection transistor, a plurality of memory cells and a ground selection transistor. The control circuit controls a program operation by precharging channels of the plurality of cell strings to a first voltage during a bit-line set-up period of a program loop, applying a program voltage to a selected word-line of the plurality of cell strings during a program execution period of the program loop and after recovering voltages of the selected word-line and unselected word-lines of the plurality of cell strings to a negative voltage smaller than a ground voltage, recovering the voltages of the selected word-line and the unselected word-lines to a second voltage greater than the ground voltage during a recovery period of the program loop.

公开(公告)号：US20220093179A1

公开(公告)日：2022-03-24

申请号：US17234955

申请日：2021-04-20

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Yohan Lee ,  Sangwan Nam ,  Sangwon Park

IPC: G11C16/16 ,  G11C16/26 ,  G11C16/30 ,  G11C16/32 ,  G11C16/08 ,  G11C16/04

Abstract: A memory device includes memory blocks, each including memory cells, and peripheral circuits that control the memory blocks and execute an erase operation for each of the memory blocks. Each memory block includes word lines stacked on a substrate, channel structures extending perpendicular to an upper surface of the substrate and penetrating through the word lines, and a source region disposed on the substrate and connected to the channel structures. During an erase operation in which an erase voltage is input to the source region of a target memory block, the peripheral circuits reduce a voltage of a first word line from a first bias voltage to a second bias voltage at a first time and reduce a voltage of a second word line, different from the first word line, from a third bias voltage to a fourth bias voltage at a second time different from the first in time.

公开(公告)号：US20210098072A1

公开(公告)日：2021-04-01

申请号：US17022967

申请日：2020-09-16

Applicant: Samsung Electronics Co., Ltd.

Inventor： Yonghyuk Choi ,  Sangwan Nam ,  Jaeduk Yu ,  Sangwon Park ,  Bongsoon Lim

IPC: G11C29/00 ,  G11C7/10 ,  G11C29/18 ,  G11C29/44 ,  G11C29/12

Abstract: A nonvolatile memory device includes memory cell region including a first metal pad and a peripheral circuit region including a second metal pad, is connected to the memory cell region by the first metal pad and the second metal pad and includes including an address decoder and a page buffer circuit located on a first substrate. A memory cell array is provided in the memory cell region, which includes a first vertical structure on a second substrate. The first vertical structure includes first sub-blocks and first via areas in which one or more through-hole vias are provided, and through-hole vias pass through the first vertical structure. A control circuit in the peripheral circuit region groups the memory blocks into a plurality of groups based on whether the memory blocks is close to the first via areas and performs address re-mapping.

公开(公告)号：US12100463B2

公开(公告)日：2024-09-24

申请号：US17954663

申请日：2022-09-28

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Bongkil Jung ,  Sangwan Nam ,  Keeho Jung

IPC: G11C29/12 ,  G11C29/02 ,  G11C29/14 ,  G11C29/20 ,  G11C16/04

CPC classification number: G11C29/12015 ,  G11C29/025 ,  G11C29/14 ,  G11C29/20 ,  G11C16/0483

Abstract: Provided are a memory device detecting a defect and an operating method thereof. The memory device includes a memory cell area including a memory cell array that stores data, and a peripheral circuit area including a control logic configured to control operations of the memory cell array, wherein the peripheral circuit area further includes a defect detection circuit, the defect detection circuit being configured to generate a count result value by selecting a first input signal from a plurality of input signals and counting at least one time interval of the first input signal based on a clock signal, and to detect a defect of the first input signal by comparing an expected value with the count result value, and the at least one time interval is a length of time in which logic low or logic high is maintained.

公开(公告)号：US11804280B2

公开(公告)日：2023-10-31

申请号：US17749607

申请日：2022-05-20

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Sehwan Park ,  Jinyoung Kim ,  Ilhan Park ,  Kyoman Kang ,  Sangwan Nam

IPC: G11C29/50 ,  G11C16/28 ,  G11C7/10 ,  G11C8/18 ,  G11C29/44 ,  G11C29/12

CPC classification number: G11C29/50004 ,  G11C7/1039 ,  G11C7/1045 ,  G11C7/1057 ,  G11C7/1084 ,  G11C8/18 ,  G11C16/28 ,  G11C29/44 ,  G11C2029/1202 ,  G11C2029/1204

Abstract: A non-volatile memory device includes a memory cell array including a plurality of memory blocks that includes a plurality of memory cells connected to a plurality of word lines and a plurality of bit lines, a row decoder configured to select one among the plurality of memory blocks, based on an address, a voltage generator configured to apply word line voltages corresponding to selected word lines and unselected word lines, among the plurality of word lines, page buffers connected to the plurality of bit lines and configured to read data from a memory cell connected to one among the selected word lines of the selected one among the plurality of memory blocks, and a control logic configured to control the row decoder, the voltage generator, and the page buffers.

公开(公告)号：US11763879B2

公开(公告)日：2023-09-19

申请号：US17322065

申请日：2021-05-17

Applicant: Samsung Electronics Co., Ltd.

Inventor： Yoonjee Kim ,  Seungyeon Kim ,  Sangwan Nam ,  Hongsoo Jeon ,  Jiho Cho

IPC: G11C11/4097 ,  G11C5/06 ,  G11C11/4093 ,  G11C11/408 ,  G11C11/4099

CPC classification number: G11C11/4097 ,  G11C5/06 ,  G11C11/4085 ,  G11C11/4087 ,  G11C11/4093 ,  G11C11/4099

Abstract: A memory device includes a peripheral circuit area including a first substrate and circuit elements on the first substrate, at least a portion of the circuit elements providing a source driver, and a cell area including a second substrate stacked with the peripheral circuit area in a first direction, perpendicular to an upper surface of the first substrate, and cell blocks and dummy blocks arranged in a second direction, parallel to an upper surface of the second substrate. Each of the cell blocks includes gate electrode layers and insulating layers alternately stacked on the second substrate, and channel structures extending in the first direction to penetrate through the gate electrode layers and the insulating layers and to be connected to the second substrate, at least one source contact block, among the dummy blocks, includes a first dummy insulating region on the second substrate, and source contacts extending in the first direction, penetrating through the first dummy insulating region and connected to the second substrate, and the source contacts are connected to the source driver through metal wirings in an upper portion of the cell area.

公开(公告)号：US20230162791A1

公开(公告)日：2023-05-25

申请号：US17825764

申请日：2022-05-26

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Hongsoo Jeon ,  Bongsoon Lim ,  Sangwan Nam

IPC: G11C16/04 ,  G11C16/08 ,  G11C16/20 ,  G11C5/06

CPC classification number: G11C16/0433 ,  G11C16/08 ,  G11C16/20 ,  G11C5/063

Abstract: A nonvolatile memory device includes a first semiconductor layer and a second semiconductor layer. The first semiconductor layer includes word-lines, at least one string selection line, at least one ground selection line, and a memory cell array including at least one memory block. The second semiconductor includes a first address decoder and a second address decoder. The first address decoder is disposed under a first extension region adjacent to a first side of a cell region and includes a plurality of first pass transistors driving the word-lines, the at least one string selection line, and the at least one ground selection line. The second address decoder is disposed under a second extension region adjacent to a second side of the cell region and includes a plurality of second pass transistors driving the at least one string selection line and the at least one ground selection line.

公开(公告)号：US11514997B2

公开(公告)日：2022-11-29

申请号：US17156801

申请日：2021-01-25

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Jinyoung Kim ,  Sehwan Park ,  Ilhan Park ,  Sangwan Nam

IPC: G11C29/42 ,  G11C29/18 ,  G11C29/44 ,  G11C29/12

Abstract: A controller including: control pins for providing control signals to a nonvolatile memory; a buffer memory configured to store first to third tables; and an error correction code (ECC) circuit configured to correct an error in first data read from the nonvolatile memory according to a first read command, wherein the first table stores first offset information, the second table stores second offset information, and the third table stores third offset information, wherein the third offset information corresponds to a history read level and is determined by the first and second offset information, and when the error of the first data is uncorrectable, an on-chip valley search operation is performed by the nonvolatile memory according to a second read command, detection information of the on-chip valley search operation is received according to a specific command, and the second offset information which corresponds to the detection information is generated.