公开(公告)号：US09362172B2

公开(公告)日：2016-06-07

申请号：US14566828

申请日：2014-12-11

Applicant: Samsung Electronics Co., Ltd.

Inventor： Kyu-Ha Lee ,  Ho-Jin Lee ,  Pil-Kyu Kang ,  Byung Lyul Park ,  Hyunsoo Chung ,  Gilheyun Choi

IPC: H01L21/768 ,  H01L23/522 ,  H01L23/48 ,  H01L25/065 ,  H01L23/00 ,  H01L23/31

CPC classification number: H01L21/76898 ,  H01L23/3128 ,  H01L23/481 ,  H01L23/5226 ,  H01L24/05 ,  H01L24/06 ,  H01L24/13 ,  H01L24/16 ,  H01L25/0657 ,  H01L2224/02372 ,  H01L2224/0401 ,  H01L2224/05548 ,  H01L2224/05567 ,  H01L2224/0557 ,  H01L2224/05572 ,  H01L2224/06181 ,  H01L2224/13022 ,  H01L2224/131 ,  H01L2224/16148 ,  H01L2224/16225 ,  H01L2224/16227 ,  H01L2225/06513 ,  H01L2225/06517 ,  H01L2225/06544 ,  H01L2225/06565 ,  H01L2924/00014 ,  H01L2924/15311 ,  H01L2924/00012 ,  H01L2924/014 ,  H01L2224/05552

Abstract: The inventive concept provides semiconductor devices having through-vias and methods for fabricating the same. The method may include forming a via-hole opened toward a top surface of a substrate and partially penetrating the substrate, forming a via-insulating layer having a first thickness on a bottom surface of the via-hole and a second thickness smaller than the first thickness on an inner sidewall of the via-hole, forming a through-via in the via-hole which the via-insulating layer is formed in, and recessing a bottom surface of the substrate to expose the through-via. Forming the via-insulating layer may include forming a flowable layer on the substrate, and converting the flowable layer into a first flowable chemical vapor deposition layer having the first thickness on the bottom surface of the via-hole.

公开(公告)号：US20250079424A1

公开(公告)日：2025-03-06

申请号：US18757933

申请日：2024-06-28

Applicant: Samsung Electronics Co., Ltd.

Inventor： Hyunsoo Chung ,  Kwangsoo Kim ,  Chiwoo Lee

IPC: H01L25/16 ,  G02B6/42 ,  H01L23/00 ,  H01L23/31 ,  H01L23/48

Abstract: A semiconductor package includes a redistribution layer, a photonic integrated circuit (PIC) chip on the redistribution layer, a buffer chip on the redistribution layer, an electronic integrated circuit (EIC) chip on the PIC chip and the buffer chip, and a plurality of stacked structures on the buffer chip, each of the plurality of stacked structures including a plurality of stacked semiconductor chips. The plurality of stacked structures are spaced apart from one another in a horizontal direction, and a portion of the EIC chip overlaps the PIC chip in a vertical direction, and another portion of the EIC chip overlaps the buffer chip in a vertical direction.

公开(公告)号：US20250062286A1

公开(公告)日：2025-02-20

申请号：US18588462

申请日：2024-02-27

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Hyunsoo Chung ,  Kwang-Soo Kim ,  Jun Gul Hwang

IPC: H01L25/065 ,  H01L21/56 ,  H01L23/00 ,  H01L23/31 ,  H01L23/48 ,  H10B80/00

Abstract: A semiconductor package includes a first semiconductor chip having a front side and a back side that is opposite to the front side, the first semiconductor chip includes a front side wiring structure disposed on the front side, a back side wiring structure disposed on the back side, and a first through via electrically connected to the front side wiring structure and the back side wiring structure, a second semiconductor chip disposed on the back side of the first semiconductor chip and including a second through via, and a third semiconductor chip disposed on the front side of the first semiconductor chip, wherein the first semiconductor chip receives power through the second through via, and wherein a thickness of the second semiconductor chip is greater than a thickness of the first semiconductor chip.

公开(公告)号：US20250046749A1

公开(公告)日：2025-02-06

申请号：US18783805

申请日：2024-07-25

Applicant: Samsung Electronics Co., Ltd.

Inventor： Hyunsoo Chung ,  Kwangsoo Kim ,  Inhyo Hwang

IPC: H01L23/00 ,  H01L23/31 ,  H01L23/498 ,  H01L23/538 ,  H01L25/18 ,  H10B80/00

Abstract: A semiconductor package includes an interposer; a plurality of semiconductor devices that are on the interposer and spaced apart from each other; and a package underfill layer that includes a first underfill layer in a first gap that is between the plurality of semiconductor devices and a second underfill layer in a second gap that is between the plurality of semiconductor devices and the interposer, where the second underfill layer includes a second underfill layer side surface that faces a lateral direction, where the second underfill layer side surface does not contact the plurality of semiconductor devices and a portion of the interposer that is adjacent to the second gap, where the second underfill layer side surface extends between a top surface of the interposer and bottom surfaces of the plurality of semiconductor devices and extends from a lower outer boundary.

公开(公告)号：US20250022843A1

公开(公告)日：2025-01-16

申请号：US18428633

申请日：2024-01-31

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Hyunsoo Chung ,  Jaesic Lee ,  Inhyo Hwang

IPC: H01L25/065 ,  H01L23/00 ,  H01L23/29 ,  H01L23/31 ,  H01L23/367 ,  H01L23/373 ,  H01L25/00 ,  H01L25/18

Abstract: Provided a semiconductor package including a redistribution structure, a semiconductor structure on the redistribution structure, a plurality of semiconductor stacking structures on the redistribution structure, the plurality of semiconductor stacking structures being adjacent to the semiconductor structure, and a height of each of the plurality of semiconductor stacking structures being greater than a height of the semiconductor structure, and a heat dissipation structure on the semiconductor structure, the heat dissipation structure including a plurality of through openings, wherein each semiconductor stacking structure among the plurality of semiconductor stacking structures is positioned within a corresponding through opening among the plurality of through openings, and wherein an upper surface of each of the plurality of semiconductor stacking structures is exposed through the corresponding through opening.

公开(公告)号：US12154889B2

公开(公告)日：2024-11-26

申请号：US17370594

申请日：2021-07-08

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Hyunsoo Chung ,  Taewon Yoo ,  Myungkee Chung ,  Jinchan Ahn

IPC: H01L23/64 ,  H01L23/00 ,  H01L23/498 ,  H01L25/10

Abstract: Disclosed is a semiconductor package comprising a semiconductor chip and a redistribution layer. The semiconductor chip includes a semiconductor substrate, a passivation layer, and first power, second power, and signal pads exposed from the passivation layer. The redistribution layer includes a photosensitive dielectric layer, and first to third redistribution patterns and a high-k dielectric pattern that are in the photosensitive dielectric layer. The first, second, and third redistribution patterns are respectively connected to the first power, second power, and signal pads. The high-k dielectric pattern is between the first and second redistribution patterns. The photosensitive dielectric layer includes a first dielectric material. The high-k dielectric pattern includes a second dielectric material whose dielectric constant greater than that of the first dielectric material. The high-k dielectric pattern is in contact with the passivation layer. The passivation layer includes a dielectric material different from the first and second dielectric materials.

公开(公告)号：US20240332200A1

公开(公告)日：2024-10-03

申请号：US18737527

申请日：2024-06-07

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Young Lyong Kim ,  Hyunsoo Chung ,  Inhyo Hwang

IPC: H01L23/538 ,  H01L23/31 ,  H01L25/065

CPC classification number: H01L23/5385 ,  H01L23/3114 ,  H01L23/5384 ,  H01L23/5386 ,  H01L25/0655

Abstract: A semiconductor package includes a package substrate with a first vent hole, a first semiconductor chip mounted the package substrate, an interposer including supporters on a bottom surface of the interposer and a second vent hole, wherein the supporters contact a top surface of the first semiconductor chip, and the interposer is electrically connected to the package substrate through connection terminals. The semiconductor package further include a second semiconductor chip mounted on the interposer, and a molding layer disposed on the package substrate to cover the first semiconductor chip, the interposer, and the second semiconductor chip.

公开(公告)号：US11923292B2

公开(公告)日：2024-03-05

申请号：US17307212

申请日：2021-05-04

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Jinkuk Bae ,  Hyunsoo Chung ,  Inyoung Lee ,  Donghyeon Jang

IPC: H01L23/522 ,  H01L21/768 ,  H01L23/00 ,  H01L23/31

CPC classification number: H01L23/5226 ,  H01L21/76873 ,  H01L23/3128 ,  H01L24/09 ,  H01L24/17

Abstract: A semiconductor device includes a semiconductor substrate, a conductive pad disposed on the semiconductor substrate, and a pillar pattern disposed on the conductive pad. The semiconductor device further includes a solder seed pattern disposed on the pillar pattern, and a solder portion disposed on the pillar pattern and the solder seed pattern. A first width of the solder seed pattern is less than a second width of a top surface of the pillar pattern.

公开(公告)号：US20230144602A1

公开(公告)日：2023-05-11

申请号：US17977100

申请日：2022-10-31

Applicant: Samsung Electronics Co., Ltd.

Inventor： Younglyong Kim ,  Hyunsoo Chung ,  Inhyo Hwang

IPC: H01L25/065 ,  H01L23/00 ,  H01L23/31

CPC classification number: H01L25/0657 ,  H01L23/3128 ,  H01L24/29 ,  H01L24/32 ,  H01L24/48 ,  H01L24/45 ,  H01L24/73 ,  H01L2224/29186 ,  H01L2224/32145 ,  H01L2224/32225 ,  H01L2224/45139 ,  H01L2224/45144 ,  H01L2224/48145 ,  H01L2224/48227 ,  H01L2224/73265 ,  H01L2225/0651 ,  H01L2225/06506 ,  H01L2225/06562

Abstract: The semiconductor package, includes: a package substrate; a substrate adhesive member on the package substrate; a plurality of semiconductor chips stacked on the substrate adhesive member and including first and second semiconductor chips; and a conductive connection member connecting the package substrate and the semiconductor chips, each of the semiconductor chips including a semiconductor chip body, a chip pad, an upper oxide layer comprised of a first material and covering an upper surface of the semiconductor chip body and exposing a portion of an upper surface of the chip pad, and a lower oxide layer comprised of a second material and covering a lower surface of the semiconductor chip body, wherein the upper oxide layer of the first semiconductor chip has an oxide bonding region between the first material and the second material in a first region in contact with the lower oxide layer of the second semiconductor chip.

公开(公告)号：US11574819B2

公开(公告)日：2023-02-07

申请号：US17188404

申请日：2021-03-01

Applicant: Samsung Electronics Co., Ltd.

Inventor： Chanho Lee ,  Hyunsoo Chung ,  Hansung Ryu ,  InYoung Lee

IPC: H01L21/50 ,  H01L23/48 ,  H01L23/00 ,  H01L23/58 ,  H01L23/373 ,  H01L21/48 ,  H01L21/02 ,  H01L23/544 ,  H01L25/065 ,  H01L21/768 ,  H01L23/31

Abstract: A semiconductor device including a substrate, an insulating layer on the substrate and including a trench, at least one via structure penetrating the substrate and protruding above a bottom surface of the trench, and a conductive structure surrounding the at least one via structure in the trench may be provided.