公开(公告)号：US11955470B2

公开(公告)日：2024-04-09

申请号：US17229062

申请日：2021-04-13

Applicant: Samsung Electronics Co., Ltd.

Inventor： Jiwon Kim ,  Jaeho Ahn ,  Sungmin Hwang ,  Joonsung Lim ,  Sukkang Sung

IPC: H01L23/00 ,  H01L25/18 ,  H10B41/10 ,  H10B41/27 ,  H10B41/35 ,  H10B41/40 ,  H10B43/10 ,  H10B43/27 ,  H10B43/35 ,  H10B43/40

CPC classification number: H01L25/18 ,  H01L24/08 ,  H10B41/10 ,  H10B41/27 ,  H10B41/35 ,  H10B41/40 ,  H10B43/10 ,  H10B43/27 ,  H10B43/35 ,  H10B43/40 ,  H01L2224/08147 ,  H01L2924/1431 ,  H01L2924/1438

Abstract: A semiconductor device includes a first peripheral circuit region comprising a plurality of lower circuitries, a second peripheral circuit region apart from the first peripheral circuit region in a vertical direction, the second peripheral circuit region comprising a plurality of upper circuitries, and a cell region comprising a plurality of word lines, the cell region between the first peripheral circuit region and the second peripheral circuit region in the vertical direction. The plurality of word lines comprise a first word line connected to a first lower circuitry selected from the plurality of lower circuitries and a second word line connected to a first upper circuitry selected from the plurality of upper circuitries.

公开(公告)号：US11935597B2

公开(公告)日：2024-03-19

申请号：US17523337

申请日：2021-11-10

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Jaeho Ahn ,  Jiwon Kim ,  Sungmin Hwang ,  Joonsung Lim ,  Sukkang Sung

IPC: G11C16/04 ,  G11C16/10 ,  G11C16/26 ,  H01L23/48 ,  H10B41/27 ,  H10B41/35 ,  H10B41/40 ,  H10B43/27 ,  H10B43/35 ,  H10B43/40

CPC classification number: G11C16/10 ,  G11C16/26 ,  H01L23/481 ,  H10B41/27 ,  H10B41/35 ,  H10B41/40 ,  H10B43/27 ,  H10B43/35 ,  H10B43/40

Abstract: A semiconductor memory device includes: a semiconductor substrate having a first surface and a second surface opposing each other; a back-side insulating layer below the second surface of the semiconductor substrate; an external input/output conductive pattern below the back-side insulating layer; a circuit device including a gate electrode and a source/drain region, on the first surface of the semiconductor substrate; an internal input/output conductive pattern on the first surface of the semiconductor substrate, the internal input/output conductive pattern having at least a portion disposed on the same level as at least a portion of the gate electrode; a through-electrode structure penetrating through the semiconductor substrate and the back-side insulating layer and electrically connected to the internal input/output conductive pattern and the external input/output conductive pattern; and a memory cell array region disposed on a level higher than the circuit device, on the first surface of the semiconductor substrate.

公开(公告)号：US20230422523A1

公开(公告)日：2023-12-28

申请号：US18180366

申请日：2023-03-08

Applicant: Samsung Electronics Co., Ltd.

Inventor： Jiwon Kim ,  Dohyung Kim ,  Jiyoung Kim ,  Sukkang Sung

IPC: H10B80/00 ,  H10B43/27

CPC classification number: H10B80/00 ,  H10B43/27

Abstract: A three-dimensional semiconductor memory device includes a first substrate, a peripheral circuit structure on the first substrate, and a cell array structure on the peripheral circuit structure. The cell array structure includes a stacked structure including gate electrodes extending in a first direction, a source structure on the stacked structure, and a second substrate in contact with the source structure. The source structure includes a first source conductive pattern between the second substrate and the stacked structure and a second source conductive pattern on the first source conductive pattern. The second source conductive pattern includes a first source part between the first source conductive pattern and the second substrate, a source connection part passing through the second substrate and extending in the first direction, and a second source part on the second substrate and connected to the first source part through the source connection part.

公开(公告)号：US11437300B2

公开(公告)日：2022-09-06

申请号：US16989017

申请日：2020-08-10

Applicant: Samsung Electronics Co., Ltd.

Inventor： Woosung Yang ,  Jiyoung Kim ,  Jiwon Kim

IPC: H01L23/48 ,  H01L27/11582 ,  H01L27/11575 ,  H01L27/11573

Abstract: A semiconductor device includes a substrate including a cell region and a connection region. The connection region includes a plurality of pad regions and a through electrode region. A horizontal conductive layer is on the substrate. A supporter is on the horizontal conductive layer. The supporter includes a first portion in the cell region, a second portion in the plurality of pad regions, and a third portion in the through electrode region. A connection conductive layer is between the first portion and the horizontal conductive layer. A connection mold layer is between the third portion and the horizontal conductive layer. A first buried insulation layer passing through the third portion, the connection mold layer, and the horizontal conductive layer is provided. A stacked structure is on the substrate. A through electrode passing through the first buried insulation layer is provided.

公开(公告)号：US20210149195A1

公开(公告)日：2021-05-20

申请号：US17095872

申请日：2020-11-12

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Daesu CHOI ,  Jigwang Kim ,  Jiwon Kim ,  Jaemin Soh ,  Kyehoon Lee ,  Sanghoon Lee

IPC: G02B27/01 ,  G02B17/00 ,  G02B5/10

Abstract: A display apparatus and a display control method are provided. The display apparatus includes: an image source configured to output a first image; a relay optics component configured to change a size of the first image and to transfer the first image; a surrounding structure provided around the image source or the relay optics component, and including a second image of a surrounding object; and a combiner configured to form a first virtual image by reflecting the first image, and to form a second virtual image around the first virtual image by reflecting the second image.

公开(公告)号：US12236075B2

公开(公告)日：2025-02-25

申请号：US18364228

申请日：2023-08-02

Applicant: Samsung Electronics Co., Ltd.

Inventor： Jiwon Kim ,  Yujin Lim

IPC: G06F3/04845 ,  G06F1/16

Abstract: An electronic device is provided. The electronic device includes a camera, a flexible display having a display region with a changeable size, and a processor configured to display an image obtained via the camera in a first region of the display region, display at least a part of control objects related to the camera in a second region different from the first region, in case that reduction of the display region is detected, compare a size of the reduced display region to a size of the image, and display the image in the reduced display region while maintaining an aspect ratio and the size of the image such that at least a part of the control objects related to the camera overlaps the image displayed in the reduced display region.

公开(公告)号：US12217800B2

公开(公告)日：2025-02-04

申请号：US18591728

申请日：2024-02-29

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Jaeho Ahn ,  Jiwon Kim ,  Sungmin Hwang ,  Joonsung Lim ,  Sukkang Sung

IPC: G11C16/10 ,  G11C16/26 ,  H01L23/48 ,  H10B41/27 ,  H10B41/35 ,  H10B41/40 ,  H10B43/27 ,  H10B43/35 ,  H10B43/40

Abstract: A semiconductor memory device includes: a semiconductor substrate having a first surface and a second surface opposing each other; a back-side insulating layer below the second surface of the semiconductor substrate; an external input/output conductive pattern below the back-side insulating layer; a circuit device including a gate electrode and a source/drain region, on the first surface of the semiconductor substrate; an internal input/output conductive pattern on the first surface of the semiconductor substrate, the internal input/output conductive pattern having at least a portion disposed on the same level as at least a portion of the gate electrode; a through-electrode structure penetrating through the semiconductor substrate and the back-side insulating layer and electrically connected to the internal input/output conductive pattern and the external input/output conductive pattern; and a memory cell array region disposed on a level higher than the circuit device, on the first surface of the semiconductor substrate.

公开(公告)号：US20240249775A1

公开(公告)日：2024-07-25

申请号：US18591728

申请日：2024-02-29

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Jaeho Ahn ,  Jiwon Kim ,  Sungmin Hwang ,  Joonsung Lim ,  Sukkang Sung

IPC: G11C16/10 ,  G11C16/26 ,  H01L23/48 ,  H10B41/27 ,  H10B41/35 ,  H10B41/40 ,  H10B43/27 ,  H10B43/35 ,  H10B43/40

CPC classification number: G11C16/10 ,  G11C16/26 ,  H01L23/481 ,  H10B41/27 ,  H10B41/35 ,  H10B41/40 ,  H10B43/27 ,  H10B43/35 ,  H10B43/40

Abstract: A semiconductor memory device includes: a semiconductor substrate having a first surface and a second surface opposing each other; a back-side insulating layer below the second surface of the semiconductor substrate; an external input/output conductive pattern below the back-side insulating layer; a circuit device including a gate electrode and a source/drain region, on the first surface of the semiconductor substrate; an internal input/output conductive pattern on the first surface of the semiconductor substrate, the internal input/output conductive pattern having at least a portion disposed on the same level as at least a portion of the gate electrode; a through-electrode structure penetrating through the semiconductor substrate and the back-side insulating layer and electrically connected to the internal input/output conductive pattern and the external input/output conductive pattern; and a memory cell array region disposed on a level higher than the circuit device, on the first surface of the semiconductor substrate.

公开(公告)号：US20220399368A1

公开(公告)日：2022-12-15

申请号：US17701304

申请日：2022-03-22

Applicant: Samsung Electronics Co., Ltd.

Inventor： Jiwon Kim ,  Sangdon Lee ,  Sungmin Hwang ,  Sukkang Sung

IPC: H01L27/11582 ,  H01L27/11519 ,  H01L27/11524 ,  H01L27/11556 ,  H01L27/11565 ,  H01L27/1157 ,  H01L23/48

Abstract: A semiconductor device includes a stack structure, first separation patterns passing through the stack structure, a second separation pattern passing through at least a portion of the stack structure between the first separation patterns, and a cutting channel structure passing through the stack structure and having an end portion partially cut by the second separation pattern. A channel layer of the cutting channel structure has a ring shape cut by the second separation pattern to have end portions of the channel layer which are spaced apart from each other.

公开(公告)号：US11296102B2

公开(公告)日：2022-04-05

申请号：US16858983

申请日：2020-04-27

Applicant: Samsung Electronics Co., Ltd.

Inventor： Sung-Min Hwang ,  Woosung Yang ,  Joon-Sung Lim ,  Jiyoung Kim ,  Jiwon Kim

IPC: H01L27/11556 ,  H01L27/11582 ,  H01L23/528 ,  G11C5/06 ,  G11C5/02

Abstract: Disclosed is a three-dimensional semiconductor memory device including a substrate including a cell array region and a connection region, a stack including first and second stacks sequentially stacked on the substrate, the stack having a staircase structure on the connection region, each of the first and second stacks including conductive patterns vertically stacked on the substrate, and contact plugs disposed on the connection region and respectively coupled to the conductive patterns. A bottom surface of each contact plug is located between top and bottom surfaces of a corresponding conductive pattern. In each stack, a recess depth of each contact plug varies monotonically in a stacking direction of the conductive patterns, when measured from a top surface of a corresponding conductive pattern. The contact plugs coupled to an uppermost conductive pattern of the first stack and a lowermost conductive pattern of the second stack have discrete recess depths.