公开(公告)号：US20190385964A1

公开(公告)日：2019-12-19

申请号：US16244304

申请日：2019-01-10

Applicant: Samsung Electronics Co., Ltd.

Inventor： Ju-il Choi ,  Kwangjin Moon ,  Sujeong Park ,  JuBin Seo ,  Jin Ho An ,  Dong-chan Lim ,  Atsushi Fujisaki

IPC: H01L23/00

Abstract: Disclosed is a semiconductor device including a conductive pattern on a substrate, a passivation layer on the substrate and including an opening that partially exposes the conductive pattern, and a pad structure in the opening of the passivation layer and connected to the conductive pattern. The pad structure includes a first metal layer that fills the opening of the passivation layer and has a width greater than that of the opening, and a second metal layer on the first metal layer. The first metal layer has a first thickness at an outer wall of the first metal layer, a second thickness on a top surface of the passivation layer, and a third thickness on a top surface of the conductive pattern. The second thickness is greater than the first thickness, and the third thickness is greater than the second thickness.

公开(公告)号：US20130344695A1

公开(公告)日：2013-12-26

申请号：US13966531

申请日：2013-08-14

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Dong-Chan Lim ,  Gilheyun Choi ,  Kwangjin Moon ,  Deok-Young Jung ,  Byung-Lyul Park ,  Dosun Lee

IPC: H01L21/768

CPC classification number: H01L21/76802 ,  H01L21/76898 ,  H01L23/481 ,  H01L24/11 ,  H01L24/13 ,  H01L2224/0401 ,  H01L2224/05025 ,  H01L2224/1147 ,  H01L2224/13025 ,  H01L2224/13082 ,  H01L2224/13099 ,  H01L2224/13124 ,  H01L2224/13147 ,  H01L2224/13155 ,  H01L2924/0001 ,  H01L2924/01006 ,  H01L2924/01013 ,  H01L2924/01029 ,  H01L2924/01032 ,  H01L2924/01033 ,  H01L2924/01073 ,  H01L2924/01074 ,  H01L2924/014 ,  H01L2924/14 ,  H01L2924/00014 ,  H01L2924/00

Abstract: Provided are a semiconductor chip and a method of manufacturing the same. The semiconductor chip includes a substrate having a first side and a second side facing each other, and a through electrode being disposed in a hole penetrating the substrate, wherein an opening surrounded by the through electrode is disposed in the hole, wherein the opening comprises a first end adjacent to the first side of the substrate and a second end adjacent to the second side of the substrate

Abstract translation: 提供一种半导体芯片及其制造方法。 半导体芯片包括具有彼此相对的第一侧和第二侧的基板，以及设置在穿透基板的孔中的贯通电极，其中，由贯通电极包围的开口设置在孔中，其中，开口包括 与基板的第一侧相邻的第一端和与基板的第二侧相邻的第二端

公开(公告)号：US12046538B2

公开(公告)日：2024-07-23

申请号：US18354068

申请日：2023-07-18

Applicant: Samsung Electronics Co., Ltd.

Inventor： Sonkwan Hwang ,  Taeseong Kim ,  Hoonjoo Na ,  Kwangjin Moon ,  Hyungjun Jeon

IPC: H01L21/00 ,  H01L21/768 ,  H01L23/48 ,  H01L23/528 ,  H01L25/065 ,  H01L27/088 ,  H01L23/00

CPC classification number: H01L23/481 ,  H01L21/76898 ,  H01L23/528 ,  H01L25/0657 ,  H01L27/0886 ,  H01L24/02 ,  H01L24/05 ,  H01L24/06 ,  H01L2224/02381 ,  H01L2224/0401 ,  H01L2224/05569 ,  H01L2224/0557 ,  H01L2224/0603 ,  H01L2224/06181 ,  H01L2225/06513 ,  H01L2225/06544

Abstract: A semiconductor device including a semiconductor substrate, an integrated circuit layer on the semiconductor substrate, first to nth metal wiring layers (where n is a positive integer) sequentially stacked on the semiconductor substrate and the integrated circuit layer, a first through via structure extending in a vertical direction toward the semiconductor substrate from a first via connection metal wiring layer, which is one of the second to nth metal wiring layers other than the first metal wiring layer, and passing through the semiconductor substrate, and a second through via structure being apart from the first through via structure, extending in a vertical direction toward the semiconductor substrate from a second via connection metal wiring layer, which is one of the second to nth metal wiring layers other than the first metal wiring layer, and passing through the semiconductor substrate may be provided.

公开(公告)号：US20240243102A1

公开(公告)日：2024-07-18

申请号：US18410644

申请日：2024-01-11

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Yikoan Hong ,  Seokho Kim ,  Kwangjin Moon

IPC: H01L25/065 ,  H01L23/00 ,  H01L23/31 ,  H01L23/498 ,  H01L23/544 ,  H10B80/00

CPC classification number: H01L25/0657 ,  H01L23/3135 ,  H01L23/49822 ,  H01L23/544 ,  H01L24/16 ,  H01L24/32 ,  H01L24/73 ,  H01L24/96 ,  H01L24/97 ,  H10B80/00 ,  H01L24/08 ,  H01L2223/5446 ,  H01L2224/08225 ,  H01L2224/16148 ,  H01L2224/32145 ,  H01L2224/73204 ,  H01L2224/96 ,  H01L2224/97 ,  H01L2225/06513 ,  H01L2225/06541 ,  H01L2225/06555 ,  H01L2924/1431 ,  H01L2924/1436 ,  H01L2924/1811

Abstract: Provided is a semiconductor package including a first semiconductor chip, at least one second semiconductor chip on a top surface of the first semiconductor chip, a molding layer on the at least one second semiconductor chip, and a marking layer on at least one side of the molding layer, the marking layer including a hydrophobic material, wherein inner sidewalls of the marking layer contact a lower portion of sidewalls of the molding layer.

公开(公告)号：US11955408B2

公开(公告)日：2024-04-09

申请号：US17036145

申请日：2020-09-29

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Sohye Cho ,  Pilkyu Kang ,  Kwangjin Moon ,  Taeseong Kim

IPC: H01L23/48 ,  H01L21/768 ,  H01L23/50 ,  H01L23/528 ,  H10B10/00

CPC classification number: H01L23/481 ,  H01L21/76898 ,  H01L23/5286 ,  H10B10/12 ,  H01L23/50

Abstract: An integrated circuit semiconductor device includes a substrate including a first surface and a second surface opposite the first surface, a trench in the substrate, the trench extending from the first surface of the substrate toward the second surface of the substrate, a through silicon via (TSV) landing part in the trench, the TSV landing part having a first portion spaced apart from the first surface of the substrate, and a second portion between the first portion and the first surface of the substrate, the first portion being wider than the second portion, a TSV hole in the substrate, the TSV hole extending from the second surface of the substrate and aligned with a bottom surface of the TSV landing part, and a TSV in the TSV hole and in contact with the bottom surface of the TSV landing part.

公开(公告)号：US11694980B2

公开(公告)日：2023-07-04

申请号：US17709856

申请日：2022-03-31

Applicant: Samsung Electronics Co., Ltd.

Inventor： Hyungjun Jeon ,  Kwangjin Moon ,  Hakseung Lee ,  Hyoukyung Cho

IPC: H01L21/683 ,  H01L23/00 ,  H01L25/065 ,  H01L21/78 ,  H01L25/00

CPC classification number: H01L24/08 ,  H01L21/6835 ,  H01L21/78 ,  H01L24/80 ,  H01L25/0657 ,  H01L25/50 ,  H01L2221/68327 ,  H01L2224/08145 ,  H01L2224/80006 ,  H01L2224/80895 ,  H01L2224/80896

Abstract: A semiconductor stack and a method for manufacturing the same are disclosed. The semiconductor stack includes a lower chip, an upper chip disposed over the lower chip, an upper lateral-side passivation layer surrounding side surfaces of the upper chip, and a plurality of bonding pads and a bonding passivation layer disposed between the upper chip and the lower chip.

公开(公告)号：US11538782B2

公开(公告)日：2022-12-27

申请号：US17108140

申请日：2020-12-01

Applicant: Samsung Electronics Co., Ltd.

Inventor： Jubin Seo ,  Sujeong Park ,  Kwangjin Moon ,  Myungjoo Park

IPC: H01L23/00

Abstract: Disclosed is a semiconductor device comprising a semiconductor substrate, an under-bump pattern on the semiconductor substrate and including a first metal, a bump pattern on the under-bump pattern, and an organic dielectric layer on the semiconductor substrate and in contact with a sidewall of the bump pattern. The bump pattern includes a support pattern in contact with the under-bump pattern and having a first width, and a solder pillar pattern on the support pattern and having a second width. The first width is greater than the second width. The support pattern includes at least one of a solder material and an intermetallic compound (IMC). The intermetallic compound includes the first metal and the solder material.

公开(公告)号：US20220336330A1

公开(公告)日：2022-10-20

申请号：US17855902

申请日：2022-07-01

Applicant: Samsung Electronics Co., Ltd.

Inventor： Jinnam Kim ,  Seokho Kim ,  Hoonjoo Na ,  Kwangjin Moon

IPC: H01L23/48 ,  H01L29/06 ,  H01L29/78 ,  H01L29/66

Abstract: A semiconductor device includes a substrate having a first surface on which an active region is disposed, and a second surface opposite the first surface, a buried conductive line extending in one direction and having a portion buried in the active region, an insulating portion covering the buried conductive line, a contact structure disposed on the insulating portion and connected to the buried conductive line, a through-hole extending from the second surface to the insulating portion and exposing the buried portion of the buried conductive line, an insulating isolation film disposed on a side surface of the buried conductive line and exposing a bottom surface of the buried portion and a side surface adjacent to the bottom surface, a through-via contacting the bottom surface and the adjacent side surface of the buried conductive line, an insulating liner surrounding the through-via.

公开(公告)号：US11362067B2

公开(公告)日：2022-06-14

申请号：US16855352

申请日：2020-04-22

Applicant: Samsung Electronics Co., Ltd.

Inventor： Kyuha Lee ,  Pilkyu Kang ,  Seokho Kim ,  Hoonjoo Na ,  Kwangjin Moon ,  Jaehyung Park ,  Joohee Jang ,  Yikoan Hong

IPC: H01L25/065 ,  H01L23/00

Abstract: A method of manufacturing a semiconductor device according to example embodiments includes: sequentially forming first through third insulating layers on a substrate; forming an opening by etching the first through third insulating layers; forming a conductive layer configured in the opening; forming a fourth insulating layer in the opening after the forming of the conductive layer; and removing a portion of an edge region of the substrate after the forming of the fourth insulating layer.

公开(公告)号：US20210066123A1

公开(公告)日：2021-03-04

申请号：US16741187

申请日：2020-01-13

Applicant: Samsung Electronics Co., Ltd.

Inventor： Jaewon Hwang ,  Jinnam Kim ,  Kwangjin Moon ,  Kunsang Park ,  Myungjoo Park

IPC: H01L21/768 ,  H01L21/306 ,  H01L21/02

Abstract: Aspects of the present disclosure are related to a semiconductor device that includes a crystalline substrate having a first surface and a second surface vertically opposite each other and an insulating layer disposed on the first surface of the crystalline substrate. The device may also include an etch stop layer interposed between and contacting the crystalline substrate and the insulating layer and a conductive through via structure penetrating the crystalline substrate and the insulating layer. The device may also include an insulating separation layer disposed horizontally adjacent to the conductive through via structure, and having an inner wall and an outer wall. The insulating separation layer may include a first portion disposed between the conductive through via structure and the crystalline substrate, and a second portion disposed between the conductive through via structure and the etch stop layer.