公开(公告)号：US20190198491A1

公开(公告)日：2019-06-27

申请号：US16191720

申请日：2018-11-15

Applicant: Samsung Electronics Co., Ltd.

Inventor： Jung-Ho Do ,  Dal-Hee Lee ,  Jin-Young Lim ,  Tae-Joong Song ,  Jong-Hoon Jung

IPC: H01L27/02 ,  H01L27/088 ,  H01L21/768 ,  G11C8/16 ,  G11C11/412

CPC classification number: H01L27/0207 ,  G11C8/16 ,  G11C11/412 ,  H01L21/76895 ,  H01L27/088

Abstract: An integrated circuit may include a first active region and a second active region, and the first and second active regions may extend on a substrate in a first horizontal direction in parallel to each other and have different conductivity types from each other. A first gate line may extend in a second horizontal direction crossing the first horizontal direction, and may form a first transistor with the first active region. The first transistor may include a gate to which a first input signal is applied. The first gate line may include a first partial gate line that overlaps the first active region in a perpendicular direction and that has an end on a region between the first and second active regions.

公开(公告)号：US10311946B2

公开(公告)日：2019-06-04

申请号：US15221875

申请日：2016-07-28

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Han-Wool Jeong ,  Woo-Jin Rim ,  Tae-Joong Song ,  Seong-Ook Jung ,  Gyu-Hong Kim

IPC: G11C7/18 ,  G11C11/419 ,  G11C11/4091

Abstract: The semiconductor memory device includes: a memory cell; a sensing circuit connected to the memory cell via a first bit line and a second bit line different from the first bit line, the sensing circuit configured to sense data stored in the memory cell; and a bit line voltage control circuit connected to the memory cell via the first bit line and the second bit line, the bit line voltage control circuit configured to precharge the first bit line to a first voltage that is lower than a supply voltage and to precharge the second bit line to a second voltage that is lower than the supply voltage and is different from the first voltage.

公开(公告)号：US20190074045A1

公开(公告)日：2019-03-07

申请号：US15919876

申请日：2018-03-13

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： SUK-SOO PYO ,  Hyun-Taek Jung ,  Tae-Joong Song

IPC: G11C11/16

CPC classification number: G11C11/1697 ,  G11C8/08 ,  G11C11/1657 ,  G11C11/1659 ,  G11C11/1673 ,  G11C11/1675 ,  G11C11/1693 ,  G11C11/5607 ,  G11C13/0004 ,  G11C13/0007 ,  G11C13/0028 ,  G11C13/003 ,  G11C13/004 ,  G11C13/0061 ,  G11C13/0069 ,  G11C2013/0071 ,  G11C2213/79

Abstract: A resistive memory device includes: a voltage generator generating a write word line voltage according to activation of a write enable signal; a switch circuit outputting one of the write word line voltage and a read word line voltage in response to the write enable signal as an output voltage; a word line power path connected to the switch circuit to receive the output voltage; and a word line driver driving a word line according to a voltage applied to the word line power path, wherein a write command starts to be received after a certain delay following the activation of the write enable signal, and a write operation is performed within an activation period of the write enable signal in response to the received write command.

公开(公告)号：US10216883B2

公开(公告)日：2019-02-26

申请号：US15351545

申请日：2016-11-15

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Ha-Young Kim ,  Sung-We Cho ,  Tae-Joong Song

IPC: G06F17/50 ,  G03F1/00 ,  G03F7/00 ,  G03F7/20

Abstract: A computer-implemented method of designing an integrated circuit (IC) includes allocating a plurality of colors to a plurality of patterns corresponding to one layer of a first cell so that a multi-patterning technology is designated for use in forming the plurality of patterns, the first cell being a multi-height cell corresponding to a plurality of rows, generating a plurality of shift cells, in which a color remapping operation associated with the plurality of patterns is performed for each row, with respect to the first cell, and storing a cell set including the first cell and the plurality of shift cells in a standard cell library.

公开(公告)号：US20180173835A1

公开(公告)日：2018-06-21

申请号：US15689008

申请日：2017-08-29

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： JUNG-HO DO ,  Jong-Hoon Jung ,  Seung-Young Lee ,  Tae-Joong Song

IPC: G06F17/50

CPC classification number: G06F17/5072 ,  G03F1/70 ,  G03F7/70283 ,  G03F7/70466 ,  G06F17/5009 ,  G06F17/5068 ,  G06F17/5081

Abstract: An integrated circuit includes: a lower layer including first and second lower patterns extending in a first direction; a first via arranged on the first lower pattern, and a second via arranged on the second lower pattern; a first upper pattern arranged on the first via; and a second upper pattern arranged on the second via, a first color is assigned to the first upper pattern, a second color is assigned to the second upper pattern, the first and second upper patterns are adjacent to each other in a second direction, and the first via is arranged in a first edge region of the first lower pattern, the first edge region being farther away from the second lower pattern than a second edge region of the first lower pattern, the second edge region being opposite to the first edge region.

公开(公告)号：US09324384B2

公开(公告)日：2016-04-26

申请号：US14504596

申请日：2014-10-02

Applicant: Samsung Electronics Co., Ltd.

Inventor： Tae-Joong Song ,  Sung-Hyun Park ,  Woo-Jin Rim ,  Gi-Young Yang

IPC: G11C7/08 ,  G11C7/06 ,  G11C7/12 ,  G11C11/419

CPC classification number: G11C7/065 ,  G11C7/12 ,  G11C11/419

Abstract: In a sense amplifier, a switching transistor is configured to apply a ground voltage to a ground node in response to a sense enable signal. A first detection circuit is configured to output a first detection signal to the first detection node based on a mode signal and a voltage of a bit-line. A second detection circuit is configured to output a second detection signal to the second detection node based on a voltage of a complementary bit-line. A latch circuit is connected to a supply voltage, the first detection node and the second detection node, and configured to output a first amplified signal and a second amplified signal through a latch node and a complementary latch node, respectively, based on the first detection signal and the second detection signal.

Abstract translation: 在感测放大器中，开关晶体管被配置为响应于感测使能信号而将接地电压施加到接地节点。 第一检测电路被配置为基于位线的模式信号和电压将第一检测信号输出到第一检测节点。 第二检测电路被配置为基于互补位线的电压将第二检测信号输出到第二检测节点。 锁存电路连接到电源电压，第一检测节点和第二检测节点，并且被配置为分别基于第一检测来通过锁存节点和互补锁存器节点输出第一放大信号和第二放大信号 信号和第二检测信号。