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    Stacked type semiconductor memory device and chip selection circuit
    32.
    发明授权
    Stacked type semiconductor memory device and chip selection circuit 失效
    堆叠型半导体存储器件和芯片选择电路

    公开(公告)号：US08709871B2

    公开(公告)日：2014-04-29

    申请号：US13293897

    申请日：2011-11-10

    申请人： Junji Yamada ,  Hiroaki Ikeda ,  Kayoko Shibata ,  Yoshihiko Inoue ,  Hitoshi Miwa ,  Tatsuya Ijima

    发明人： Junji Yamada ,  Hiroaki Ikeda ,  Kayoko Shibata ,  Yoshihiko Inoue ,  Hitoshi Miwa ,  Tatsuya Ijima

    IPC分类号： H01L21/66

    CPC分类号： H01L25/0657 ,  G11C5/02 ,  G11C5/04 ,  G11C2029/4402 ,  H01L2224/16145 ,  H01L2225/06513 ,  H01L2924/01021 ,  H01L2924/15311

    摘要： A stacked type semiconductor memory device of having a structure in which a plurality of semiconductor chips is stacked and a desired semiconductor chip can be selected by assigning a plurality of chip identification numbers different from each other are individually assigned to the plurality of semiconductor chips comprising: a plurality of operation circuits which is connected in cascade in a stacking order of the plurality of semiconductor chips and outputs the plurality of identification numbers different from each other by performing a predetermined operation; and a plurality of comparison circuits which detects whether or not each the identification number and a chip selection address commonly connected to each the semiconductor chip are equal to each other by comparing them.

    摘要翻译： 通过分配彼此不同的多个芯片标识号，具有堆叠多个半导体芯片的结构和可以选择期望的半导体芯片的堆叠型半导体存储器件被分别分配给多个半导体芯片，包括： 多个操作电路，其以所述多个半导体芯片的堆叠顺序级联连接，并通过执行预定的操作输出所述多个不同的识别号码; 以及多个比较电路，通过比较它们来检测每个半导体芯片共同连接的每个识别号码和芯片选择地址是否相等。

    Semiconductor memory device and stress testing method thereof
    34.
    发明授权
    Semiconductor memory device and stress testing method thereof 有权
    半导体存储器件及其应力测试方法

    公开(公告)号：US07760573B2

    公开(公告)日：2010-07-20

    申请号：US11349091

    申请日：2006-02-08

    申请人： Kayoko Shibata ,  Hiroaki Ikeda

    发明人： Kayoko Shibata ,  Hiroaki Ikeda

    IPC分类号： G11C5/14

    CPC分类号： G11C29/12 ,  G01R31/2856 ,  G01R31/31721 ,  G11C29/12005 ,  G11C29/1201 ,  H01L25/18 ,  H01L2224/0401 ,  H01L2224/0557 ,  H01L2224/13025 ,  H01L2224/16145 ,  H01L2225/06565 ,  H01L2924/0002 ,  H01L2924/15311 ,  H01L2224/05552

    摘要： A semiconductor memory device includes a core chip having at least memory cells formed in the core chip, an interface chip having at least peripheral circuits of the memory cells formed in the interface chip, and an external terminal group. The external terminal group includes at least a core power supply terminal that is connected to an internal circuit of the core chip without being connected to an internal circuit of the interface chip, and an interface power supply terminal that is connected to an internal circuit of the interface chip without being connected to the internal circuit of the core chip. With this arrangement, mutually different operation voltages that are optimum for both chips can be given to these chips.

    摘要翻译： 半导体存储器件包括至少具有形成在芯片芯片中的存储器单元的芯片芯片，至少具有形成在接口芯片中的存储单元的外围电路的接口芯片和外部端子组。 外部端子组至少包括与芯片的内部电路连接而不连接到接口芯片的内部电路的核心电源端子，以及连接到内部电路的内部电路的接口电源端子 接口芯片不连接到核心芯片的内部电路。 利用这种布置，可以给这些芯片提供对两个芯片最佳的相互不同的操作电压。

    Memory module and memory system
    36.
    发明授权
    Memory module and memory system 有权
    内存模块和内存系统

    公开(公告)号：US07411806B2

    公开(公告)日：2008-08-12

    申请号：US11634405

    申请日：2006-12-06

    申请人： Seiji Funaba ,  Yoji Nishio ,  Kayoko Shibata

    发明人： Seiji Funaba ,  Yoji Nishio ,  Kayoko Shibata

    IPC分类号： G11C5/06 ,  G11C5/02

    CPC分类号： G11C5/04 ,  G11C5/063 ,  G11C7/1048 ,  G11C11/4093 ,  G11C2207/105 ,  H01L2224/16225 ,  H01L2924/15192 ,  H01L2924/15311 ,  H01L2924/19107

    摘要： A memory module has a plurality of DRAMs (115), which share a bus line, on the front surface and the back surface of a board. The bus line is connected through a via hole (113) from a terminal (111) to one end of a strip line (112), and the other end of the strip line is connected to a strip line in the other layer through a via hole (119) provided for looping back the line. A termination resistor (120), provided near a termination voltage terminal (VTT), is connected to the looped-back strip line in the other layer through a via hole. The DRAM terminals are connected to the strip line each through a via hole. This memory module is mounted on a motherboard, on which a memory controller is provided, through a connector. The effective characteristic impedance of the bus line is matched with the characteristic impedance of the line in the motherboard.

    摘要翻译： 存储器模块具有在板的前表面和后表面上共享总线的多个DRAM（115）。 总线通过通孔（113）从端子（111）连接到带状线（112）的一端，并且带状线的另一端通过通孔（113）连接到另一层中的带状线 孔（119）用于使线路循环。 设置在终端电压端子（VTT）附近的终端电阻器（120）通过通孔连接到另一层中的环形带状线。 DRAM端子通过通孔连接到带状线。 该存储器模块通过连接器安装在其上提供存储器控制器的母板上。 母线的有效特性阻抗与母板线路特性阻抗匹配。

    Stacked type semiconductor memory device and chip selection circuit
    38.
    发明申请
    Stacked type semiconductor memory device and chip selection circuit 失效
    堆叠型半导体存储器件和芯片选择电路

    公开(公告)号：US20070126105A1

    公开(公告)日：2007-06-07

    申请号：US11634144

    申请日：2006-12-06

    申请人： Junji Yamada ,  Hiroaki Ikeda ,  Kayoko Shibata ,  Yoshihiko Inoue ,  Hitoshi Miwa ,  Tatsuya Ijima

    发明人： Junji Yamada ,  Hiroaki Ikeda ,  Kayoko Shibata ,  Yoshihiko Inoue ,  Hitoshi Miwa ,  Tatsuya Ijima

    IPC分类号： H01L23/02

    CPC分类号： H01L25/0657 ,  G11C5/02 ,  G11C5/04 ,  G11C2029/4402 ,  H01L2224/16145 ,  H01L2225/06513 ,  H01L2924/01021 ,  H01L2924/15311

    摘要： A stacked type semiconductor memory device of having a structure in which a plurality of semiconductor chips is stacked and a desired semiconductor chip can be selected by assigning a plurality of chip identification numbers different from each other are individually assigned to the plurality of semiconductor chips comprising: a plurality of operation circuits which is connected in cascade in a stacking order of the plurality of semiconductor chips and outputs the plurality of identification numbers different from each other by performing a predetermined operation; and a plurality of comparison circuits which detects whether or not each the identification number and a chip selection address commonly connected to each the semiconductor chip are equal to each other by comparing them.

    摘要翻译： 通过分配彼此不同的多个芯片标识号，具有堆叠多个半导体芯片的结构和可以选择期望的半导体芯片的堆叠型半导体存储器件被分别分配给多个半导体芯片，包括： 多个操作电路，其以所述多个半导体芯片的堆叠顺序级联连接，并通过执行预定的操作输出所述多个不同的识别号码; 以及多个比较电路，通过比较它们来检测每个半导体芯片共同连接的每个识别号码和芯片选择地址是否相等。

    Stacked semiconductor memory device
    39.
    发明授权
    Stacked semiconductor memory device 有权
    堆叠半导体存储器件

    公开(公告)号：US07209376B2

    公开(公告)日：2007-04-24

    申请号：US11151213

    申请日：2005-06-14

    申请人： Hideaki Saito ,  Yasuhiko Hagihara ,  Muneo Fukaishi ,  Masayuki Mizuno ,  Hiroaki Ikeda ,  Kayoko Shibata

    发明人： Hideaki Saito ,  Yasuhiko Hagihara ,  Muneo Fukaishi ,  Masayuki Mizuno ,  Hiroaki Ikeda ,  Kayoko Shibata

    IPC分类号： G11C5/06

    CPC分类号： G11C5/04 ,  G11C5/063 ,  H01L25/0657 ,  H01L2224/16145 ,  H01L2225/06527 ,  H01L2225/06555 ,  H01L2924/01019 ,  H01L2924/10253 ,  H01L2924/00

    摘要： A three-dimensional semiconductor memory device having the object of decreasing the interconnection capacitance that necessitates electrical charge and discharge during data transfer and thus decreasing power consumption is provided with: a plurality of memory cell array chips, in which sub-banks that are the divisions of bank memory are organized and arranged to correspond to input/output bits, are stacked on a first semiconductor chip; and interchip interconnections for connecting the memory cell arrays such that corresponding input/output bits of the sub-banks are the same, these interchip interconnections being provided in a number corresponding to the number of input/output bits and passing through the memory cell array chips in the direction of stacking.

    摘要翻译： 具有减少在数据传送期间需要充电和放电并因此降低功耗的互连电容的目的的三维半导体存储器件具有：多个存储单元阵列芯片，其中作为分区的子行 组合存储器并且被布置为对应于输入/输出位，堆叠在第一半导体芯片上; 以及用于连接存储单元阵列的芯片间互连，使得子组的相应输入/输出位相同，这些芯片间互连以与输入/输出位数相对应的数量提供并通过存储单元阵列芯片 在堆叠的方向。