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公开(公告)号:US20150116000A1
公开(公告)日:2015-04-30
申请号:US14587588
申请日:2014-12-31
Applicant: Semiconductor Energy Laboratory Co., Ltd.
Inventor: Takeshi Aoki , Takayuki Ikeda , Yoshiyuki Kurokawa , Munehiro Kozuma
IPC: H03K19/177
CPC classification number: H03K19/1776 , H03K19/017581
Abstract: To provide a PLD having a reduced circuit area and an increased operation speed. In the circuit structure, a gate of a transistor provided between an input terminal and an output terminal of a programmable switch element is in an electrically floating state in a period when a signal is input to the programmable switch element. The structure enables the voltage of a gate to be increased by a boosting effect in response to a signal supplied from programmable logic elements, suppressing a reduction in amplitude voltage. This can reduce a circuit area by a region occupied by a booster circuit such as a pull-up circuit and increase operation speed.
Abstract translation: 提供具有减小的电路面积和增加的操作速度的PLD。 在电路结构中,设置在可编程开关元件的输入端子和输出端子之间的晶体管的栅极在信号被输入到可编程开关元件的时段内处于电浮动状态。 该结构使得能够响应于从可编程逻辑元件提供的信号的升压效应来增加栅极的电压,从而抑制幅度电压的降低。 这可以通过诸如上拉电路的升压电路占据的区域来减小电路面积,并且增加操作速度。
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公开(公告)号:US20140285234A1
公开(公告)日:2014-09-25
申请号:US14217628
申请日:2014-03-18
Applicant: SEMICONDUCTOR ENERGY LABORATORY CO., LTD.
Inventor: Munehiro Kozuma , Yoshiyuki Kurokawa
IPC: H03K19/00
CPC classification number: H03K19/0013
Abstract: To provide a charge pump circuit to manufacture a low-power-consumption PLD. A semiconductor device includes a first circuit and a second circuit electrically connected to the first circuit. A charge pump circuit formed of a transistor including an oxide semiconductor and a boosting control circuit controlling the charge pump circuit are provided between the first circuit and the second circuit. The first circuit and the charge pump circuit operate at first power supply voltage, and the boosting control circuit and the second circuit operate at second power supply voltage. The first power supply voltage is lower than the second power supply voltage.
Abstract translation: 提供电荷泵电路来制造低功耗PLD。 半导体器件包括电连接到第一电路的第一电路和第二电路。 在第一电路和第二电路之间设置由包括氧化物半导体的晶体管和控制电荷泵电路的升压控制电路构成的电荷泵电路。 第一电路和电荷泵电路在第一电源电压下工作,并且升压控制电路和第二电路在第二电源电压下工作。 第一电源电压低于第二电源电压。
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公开(公告)号:US12040795B2
公开(公告)日:2024-07-16
申请号:US17413791
申请日:2019-12-10
Applicant: Semiconductor Energy Laboratory Co., Ltd.
Inventor: Hiroki Inoue , Munehiro Kozuma , Takeshi Aoki , Shuji Fukai , Fumika Akasawa , Shintaro Harada , Sho Nagao
IPC: H03K19/094 , H01L27/06
CPC classification number: H03K19/094 , H01L27/0629
Abstract: A semiconductor device using unipolar transistors, in which high and low levels are expressed using high and low power supply potentials, is provided. The semiconductor device includes four transistors, two capacitors, two wirings, two input terminals, and an output terminal. A source or a drain of the first transistor and a source or a drain of the fourth transistor are electrically connected to the first wiring. A gate of the fourth transistor is electrically connected to the first input terminal, and a gate of the second transistor is electrically connected to the second input terminal. A source or a drain of the second transistor and a source or a drain of the third transistor are electrically connected to the second wiring. The first transistor, the second transistor, and the two capacitors are electrically connected to the output terminal.
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公开(公告)号:US11990778B2
公开(公告)日:2024-05-21
申请号:US17258957
申请日:2019-06-27
Applicant: SEMICONDUCTOR ENERGY LABORATORY CO., LTD.
Inventor: Takayuki Ikeda , Munehiro Kozuma , Takanori Matsuzaki , Ryota Tajima , Shunpei Yamazaki , Yuki Okamoto
CPC classification number: H02J7/0031 , H01M10/4235 , H02J7/0036
Abstract: Safety is secured in such a manner that an anomaly of a secondary battery is detected with a protection circuit, for example, a phenomenon that lowers the safety of a secondary battery, particularly a micro short circuit, is detected early, and users are warned or the use of the secondary battery is stopped. A secondary battery protection circuit includes a first memory circuit electrically connected to a secondary battery, a comparison circuit electrically connected to the first memory circuit, a second memory circuit electrically connected to the comparison circuit, and a power-off switch electrically connected to the second memory circuit. The power-off switch is electrically connected to the secondary battery, and the first memory circuit includes a first transistor including an oxide semiconductor and retains a voltage value of the secondary battery in an analog manner.
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公开(公告)号:US11791640B2
公开(公告)日:2023-10-17
申请号:US17298698
申请日:2019-12-05
Applicant: Semiconductor Energy Laboratory Co., Ltd.
Inventor: Munehiro Kozuma , Takayuki Ikeda
CPC classification number: H02J7/00306 , H01M10/44 , H01M10/48 , H02J7/0031 , H02J7/0047 , H01M2220/20
Abstract: Rapid degradation an off-leakage current in an overdischarged state is prevented. In order to prevent an overdischarged state, a control circuit with low leakage current includes a transistor using an oxide semiconductor, whereby the characteristics of the secondary battery are retained. In addition, a system in which a control signal generation circuit is also integrated is formed. With this system structure, the control circuit enters a low-power consumption mode in accordance with the circuit operation after an overdischarge is detected. When recovering from an overdischarged state, the control circuit enters a normally-operating mode in accordance with the voltage increase when charging is started.
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公开(公告)号:US10230368B2
公开(公告)日:2019-03-12
申请号:US15191763
申请日:2016-06-24
Applicant: Semiconductor Energy Laboratory Co., Ltd.
Inventor: Munehiro Kozuma , Yoshiyuki Kurokawa , Takayuki Ikeda , Takeshi Aoki
IPC: H03K19/00 , H03K19/173 , H03K19/177 , H01L27/12 , H01L29/786 , H03K19/0944 , H01L29/24
Abstract: A programmable logic device includes a plurality of programmable logic elements (PLE) whose electrical connection is controlled by first configuration data. Each of The PLEs includes an LUT in which a relationship between a logic level of an input signal and a logic level of an output signal is determined by second configuration data, an FF to which the output signal of the LUT is input, and an MUX. The MUX includes at least two switches each including first and second transistor. A signal including third configuration data is input to a gate of the second transistor through the first transistor. The output signal of the LUT or an output signal of the FF is input to one of a source and a drain of the second transistor.
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公开(公告)号:US10177767B2
公开(公告)日:2019-01-08
申请号:US15345761
申请日:2016-11-08
Applicant: Semiconductor Energy Laboratory Co., Ltd.
Inventor: Munehiro Kozuma
IPC: H03K19/0175 , H03K19/177
Abstract: A semiconductor device includes a configuration memory that has functions of holding configuration data and generating a signal based on the configuration data, a context generator that has a function of generating a signal for controlling context switch, a clock generator that has a function of operating in a first mode or a second mode in accordance with the signal generated in the configuration memory, and a PLD. A clock signal is input to the context generator and the clock generator. The clock generator outputs the clock signal to the PLD in the first mode and stops outputting the clock signal to the PLD in the second mode.
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公开(公告)号:US10141054B2
公开(公告)日:2018-11-27
申请号:US15232106
申请日:2016-08-09
Applicant: Semiconductor Energy Laboratory Co., Ltd.
Inventor: Takeshi Aoki , Munehiro Kozuma , Yoshiyuki Kurokawa
Abstract: A semiconductor device that has a long data retention time during stop of supply of power supply voltage by reducing leakage current due to miniaturization of a semiconductor element. In a structure where charge corresponding to data is held with the use of low off-state current of a transistor containing an oxide semiconductor in its channel formation region, a transistor for reading data and a transistor for storing charge are separately provided, thereby decreasing leakage current flowing through a gate insulating film.
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公开(公告)号:US10027324B2
公开(公告)日:2018-07-17
申请号:US15471516
申请日:2017-03-28
Applicant: Semiconductor Energy Laboratory Co., Ltd.
Inventor: Munehiro Kozuma , Yoshiyuki Kurokawa
IPC: G06F7/38 , H03K19/00 , H03K19/177 , H03K21/02
Abstract: Skew of a multi-context PLD in context switch is reduced to achieve low power consumption. The frequency of a clock signal is switched in context switch operation in accordance with circuit operation to secure time required for context switch. By returning the frequency of the clock signal to the original frequency after executing the context switch, the PLD can maintain high-speed processing and perform the context switch accurately and safely. The time required for the context switch mainly depends on a hardware structure (circuit layout including a parasitic component). Thus, the reliability in the context switch can be improved when time that is equal to or longer than the longest time required for circuit change is secured.
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公开(公告)号:US10002656B2
公开(公告)日:2018-06-19
申请号:US15138318
申请日:2016-04-26
Applicant: Semiconductor Energy Laboratory Co., Ltd.
Inventor: Takayuki Ikeda , Yoshiyuki Kurokawa , Munehiro Kozuma
IPC: G11C7/16 , G11C11/24 , G11C16/04 , G11C16/10 , G11C11/404 , G11C11/405 , G11C11/4091 , H01L27/1156 , G11C27/00 , G11C27/02 , G11C11/40 , H01L21/02 , H01L23/528 , H01L27/105 , H01L27/12 , H01L29/66 , H01L29/786
CPC classification number: G11C11/24 , G11C7/16 , G11C11/40 , G11C11/404 , G11C11/405 , G11C11/4091 , G11C16/0441 , G11C16/10 , G11C27/005 , G11C27/02 , G11C27/024 , H01L21/02565 , H01L21/0262 , H01L23/528 , H01L27/1052 , H01L27/1156 , H01L27/1207 , H01L27/1225 , H01L27/1255 , H01L29/66969 , H01L29/7869 , H01L29/78693
Abstract: A semiconductor device capable of generating a signal (e.g., a potential signal or a current signal) suitable for usage environment or a purpose. The semiconductor device includes a first memory circuit, a first circuit, and a second memory circuit. The first circuit converts a digital signal input from the first memory circuit into an analog signal. The first memory circuit includes an input node, an output node, a transistor, and a capacitor. The capacitor is electrically connected to the output node. The transistor can control a conduction state between the input node and the output node. An analog signal is input to the input node from the first circuit. The transistor includes an oxide semiconductor layer where a channel formation region is formed.
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