PROGRAMMABLE LOGIC DEVICE AND SEMICONDUCTOR DEVICE
    31.
    发明申请
    PROGRAMMABLE LOGIC DEVICE AND SEMICONDUCTOR DEVICE 有权
    可编程逻辑器件和半导体器件

    公开(公告)号:US20150116000A1

    公开(公告)日:2015-04-30

    申请号:US14587588

    申请日:2014-12-31

    CPC classification number: H03K19/1776 H03K19/017581

    Abstract: To provide a PLD having a reduced circuit area and an increased operation speed. In the circuit structure, a gate of a transistor provided between an input terminal and an output terminal of a programmable switch element is in an electrically floating state in a period when a signal is input to the programmable switch element. The structure enables the voltage of a gate to be increased by a boosting effect in response to a signal supplied from programmable logic elements, suppressing a reduction in amplitude voltage. This can reduce a circuit area by a region occupied by a booster circuit such as a pull-up circuit and increase operation speed.

    Abstract translation: 提供具有减小的电路面积和增加的操作速度的PLD。 在电路结构中,设置在可编程开关元件的输入端子和输出端子之间的晶体管的栅极在信号被输入到可编程开关元件的时段内处于电浮动状态。 该结构使得能够响应于从可编程逻辑元件提供的信号的升压效应来增加栅极的电压,从而抑制幅度电压的降低。 这可以通过诸如上拉电路的升压电路占据的区域来减小电路面积,并且增加操作速度。

    SEMICONDUCTOR DEVICE
    32.
    发明申请
    SEMICONDUCTOR DEVICE 有权
    半导体器件

    公开(公告)号:US20140285234A1

    公开(公告)日:2014-09-25

    申请号:US14217628

    申请日:2014-03-18

    CPC classification number: H03K19/0013

    Abstract: To provide a charge pump circuit to manufacture a low-power-consumption PLD. A semiconductor device includes a first circuit and a second circuit electrically connected to the first circuit. A charge pump circuit formed of a transistor including an oxide semiconductor and a boosting control circuit controlling the charge pump circuit are provided between the first circuit and the second circuit. The first circuit and the charge pump circuit operate at first power supply voltage, and the boosting control circuit and the second circuit operate at second power supply voltage. The first power supply voltage is lower than the second power supply voltage.

    Abstract translation: 提供电荷泵电路来制造低功耗PLD。 半导体器件包括电连接到第一电路的第一电路和第二电路。 在第一电路和第二电路之间设置由包括氧化物半导体的晶体管和控制电荷泵电路的升压控制电路构成的电荷泵电路。 第一电路和电荷泵电路在第一电源电压下工作,并且升压控制电路和第二电路在第二电源电压下工作。 第一电源电压低于第二电源电压。

    Logic circuit formed using unipolar transistor, and semiconductor device

    公开(公告)号:US12040795B2

    公开(公告)日:2024-07-16

    申请号:US17413791

    申请日:2019-12-10

    CPC classification number: H03K19/094 H01L27/0629

    Abstract: A semiconductor device using unipolar transistors, in which high and low levels are expressed using high and low power supply potentials, is provided. The semiconductor device includes four transistors, two capacitors, two wirings, two input terminals, and an output terminal. A source or a drain of the first transistor and a source or a drain of the fourth transistor are electrically connected to the first wiring. A gate of the fourth transistor is electrically connected to the first input terminal, and a gate of the second transistor is electrically connected to the second input terminal. A source or a drain of the second transistor and a source or a drain of the third transistor are electrically connected to the second wiring. The first transistor, the second transistor, and the two capacitors are electrically connected to the output terminal.

    Semiconductor device, electronic component, and electronic device

    公开(公告)号:US10177767B2

    公开(公告)日:2019-01-08

    申请号:US15345761

    申请日:2016-11-08

    Inventor: Munehiro Kozuma

    Abstract: A semiconductor device includes a configuration memory that has functions of holding configuration data and generating a signal based on the configuration data, a context generator that has a function of generating a signal for controlling context switch, a clock generator that has a function of operating in a first mode or a second mode in accordance with the signal generated in the configuration memory, and a PLD. A clock signal is input to the context generator and the clock generator. The clock generator outputs the clock signal to the PLD in the first mode and stops outputting the clock signal to the PLD in the second mode.

    Semiconductor device, electronic component, and electronic device

    公开(公告)号:US10027324B2

    公开(公告)日:2018-07-17

    申请号:US15471516

    申请日:2017-03-28

    Abstract: Skew of a multi-context PLD in context switch is reduced to achieve low power consumption. The frequency of a clock signal is switched in context switch operation in accordance with circuit operation to secure time required for context switch. By returning the frequency of the clock signal to the original frequency after executing the context switch, the PLD can maintain high-speed processing and perform the context switch accurately and safely. The time required for the context switch mainly depends on a hardware structure (circuit layout including a parasitic component). Thus, the reliability in the context switch can be improved when time that is equal to or longer than the longest time required for circuit change is secured.

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