公开(公告)号：US20200304691A1

公开(公告)日：2020-09-24

申请号：US16838488

申请日：2020-04-02

Applicant: Semiconductor Energy Laboratory Co., Ltd.

Inventor： Takuro OHMARU

IPC: H04N5/225 ,  H01L27/146 ,  H04N5/369 ,  H04N5/3745 ,  H04N5/374 ,  H01L27/12

Abstract: Provided is a novel semiconductor device, a semiconductor device with reduced area, or a versatile semiconductor device. The semiconductor device includes a pixel portion including a first pixel, a second pixel, a third pixel, and a fourth pixel; a first switch and a second switch located outside the first to fourth pixels; a first wiring located outside the first to fourth pixels; a second wiring electrically connected to the first and second pixels; and a third wiring electrically connected to the third and fourth pixels. A first terminal of the first switch is electrically connected to the first wiring. A second terminal of the first switch is electrically connected to the second wiring. A first terminal of the second switch is electrically connected to the first wiring. A second terminal of the second switch is electrically connected to the third wiring.

公开(公告)号：US20190355770A1

公开(公告)日：2019-11-21

申请号：US16529135

申请日：2019-08-01

Applicant: Semiconductor Energy Laboratory Co., Ltd.

Inventor： Takuro OHMARU ,  Naoto KUSUMOTO ,  Kentaro HAYASHI

IPC: H01L27/146 ,  H04N5/369 ,  H04N5/3745 ,  H04N5/347 ,  H04N5/232

Abstract: An imaging device with low power consumption is provided. The pixel of the imaging device includes first and second photoelectric conversion elements, and first to fifth transistors. A cathode of the first photoelectric conversion element is electrically connected to the first transistor. An anode of a second photoelectric conversion element is electrically connected to the second transistor. Imaging data of a reference frame is obtained using the first photoelectric conversion element, and then imaging data of a difference detection frame is obtained using the second photoelectric conversion element. After the imaging data of the difference detection frame is obtained, a first potential that is a potential of a signal output from the pixel and a second potential that is a reference potential are compared. Whether or not there is a difference between the imaging data of the reference frame and the imaging data of the difference detection frame is determined using the first potential and the second potential.

公开(公告)号：US20170288541A1

公开(公告)日：2017-10-05

申请号：US15623870

申请日：2017-06-15

Applicant: Semiconductor Energy Laboratory Co., Ltd.

Inventor： Takuro OHMARU

IPC: H02M3/157

CPC classification number: H02M3/157 ,  H02M2001/0025

Abstract: A power supply circuit includes: an analog/digital converter for converting an analog signal to a digital signal; a pulse width modulation signal control circuit for generating a setting control signal varying in accordance with the difference between a reference voltage and a feedback voltage and a control signal for controlling a pulse width modulation signal, which is based on the digital signal; and a pulse width modulation signal generation circuit for generating the pulse width modulation signal, to which the count signal and the control signal are input, in which the control signal controls the duty cycle of the pulse width modulation signal, and the setting control signal controls the cycle of updating the duty cycle of the pulse width modulation signal.

公开(公告)号：US20170078606A1

公开(公告)日：2017-03-16

申请号：US15258011

申请日：2016-09-07

Applicant: Semiconductor Energy Laboratory Co., Ltd.

Inventor： Takuro OHMARU

IPC: H04N5/378 ,  H04N5/359 ,  H04N5/369 ,  H01L27/146

CPC classification number: H04N5/378 ,  H01L27/14612 ,  H01L27/14638 ,  H04N5/35581 ,  H04N5/3575 ,  H04N5/359 ,  H04N5/3698 ,  H04N5/37452

Abstract: An imaging device whose dynamic range can be wide with a simple structure is provided. In a circuit configuration and an operation method of the imaging device, whether a charge detection portion provided in a pixel is saturated with electrons is determined and an operation mode is changed depending on the determination result. First imaging data is captured first, and is read out in the case where the charge detection portion is not saturated with electrons. In the case where the charge detection portion is saturated with electrons, the saturation of the charge detection portion is eliminated and second imaging data is captured and read out.

Abstract translation: 提供一种其结构简单的动态范围广的成像装置。 在成像装置的电路配置和操作方法中，确定像素中的电荷检测部分是否饱和电子，并且根据确定结果改变操作模式。 首先捕获第一成像数据，并且在电荷检测部未饱和的情况下读出。 在充电检测部分被电子饱和的情况下，电荷检测部分的饱和度被消除，并且第二成像数据被捕获和读出。

公开(公告)号：US20170013214A1

公开(公告)日：2017-01-12

申请号：US15201768

申请日：2016-07-05

Applicant: Semiconductor Energy Laboratory Co., Ltd.

Inventor： Takuro OHMARU

IPC: H04N5/355 ,  H04N5/359 ,  H04N5/374 ,  H01L27/146

CPC classification number: H04N5/35554 ,  H01L27/14616 ,  H01L27/14665 ,  H04N5/353 ,  H04N5/3575 ,  H04N5/374 ,  H04N5/37452 ,  H04N5/37457

Abstract: An imaging device that has a high degree of freedom for exposure time and is capable of taking an image with little distortion is provided. In an n-th frame period where n is a natural number of two or more, a potential of a first charge accumulation portion is reset; the first charge accumulation portion is charged with a potential in accordance with an output of a photoelectric conversion element and simultaneously, imaging data in the (n−1)-th frame that is output in accordance with a potential of a second charge accumulation portion is read; a potential of the second charge accumulation portion is reset; a potential of the first charge accumulation portion is transferred to the second charge accumulation portion, and a potential of the second charge accumulation portion is held. Through the steps, the degree of freedom for an exposure period is increased.

Abstract translation: 提供了具有高曝光时间自由度且能够拍摄几乎没有失真的图像的成像装置。 在n为2以上的自然数的第n帧期间，第一电荷累积部的电位复位; 第一电荷累积部分根据光电转换元件的输出充电电位，并且同时，根据第二电荷累积部分的电位输出的第（n-1）帧中的成像数据是 读; 第二电荷累积部分的电位被复位; 第一电荷累积部分的电位被转移到第二电荷累积部分，并且保持第二电荷累积部分的电位。 通过这些步骤，曝光期间的自由度增加。

公开(公告)号：US20160203852A1

公开(公告)日：2016-07-14

申请号：US15072432

申请日：2016-03-17

Applicant: Semiconductor Energy Laboratory Co., Ltd.

Inventor： Naoaki TSUTSUI ,  Atsuo ISOBE ,  Wataru UESUGI ,  Takuro OHMARU

IPC: G11C11/4093

CPC classification number: G11C11/4093 ,  G11C11/24 ,  G11C11/401 ,  G11C11/403

Abstract: A memory device includes a first memory circuit including a silicon transistor, a selection circuit including a silicon transistor, and a second memory circuit including oxide semiconductor transistors and a storage capacitor, in which one terminal of the storage capacitor is connected to a portion where two oxide semiconductor transistors are connected in series, an output of the second memory circuit is connected to a second input terminal of the selection circuit, and an input of the second memory circuit is connected to a first input terminal of the selection circuit or an output terminal of the first memory circuit.

Abstract translation: 存储器件包括：第一存储器电路，包括硅晶体管，包括硅晶体管的选择电路和包括氧化物半导体晶体管和存储电容器的第二存储器电路，其中存储电容器的一个端子连接到两个 氧化物半导体晶体管串联连接，第二存储电路的输出连接到选择电路的第二输入端，第二存储电路的输入端连接到选择电路的第一输入端或输出端 的第一存储器电路。

公开(公告)号：US20150381169A1

公开(公告)日：2015-12-31

申请号：US14731606

申请日：2015-06-05

Applicant: SEMICONDUCTOR ENERGY LABORATORY CO., LTD.

Inventor： Takuro OHMARU ,  Hidetomo KOBAYASHI

IPC: H03K17/687

CPC classification number: H03K17/687 ,  G11C5/005 ,  G11C5/148 ,  G11C11/403 ,  G11C11/4076 ,  H01L27/108 ,  H01L27/1156 ,  H01L27/1207 ,  H03K3/012 ,  H03K3/356008

Abstract: A novel semiconductor device and a driving method thereof are provided. In the semiconductor device, a (volatile) node which holds data that is rewritten by arithmetic processing as appropriate and a node in which the data is stored are electrically connected through a source and a drain of a transistor whose channel is formed in an oxide semiconductor layer. The off-state current value of the transistor is extremely low. Therefore, electric charge scarcely leaks through the transistor from the latter node, and thus data can be held in the latter node even in a period during which supply of power source voltage is stopped. In the semiconductor device, a means of setting the potential of the latter node to a predetermined potential is provided. Specifically, a means of supplying a potential corresponding to “1” or “0” that is data stored in the latter node from the former node is provided.

Abstract translation: 提供了一种新颖的半导体器件及其驱动方法。 在半导体器件中，通过适当的算术处理保存的数据和存储数据的节点的（易失性）节点通过其沟道形成在氧化物半导体中的晶体管的源极和漏极电连接 层。 晶体管的截止电流值极低。 因此，即使在停止供给电源电压的期间，电荷几乎不会从后一个节点通过晶体管泄漏，因此数据也可以被保持在后一个节点中。 在半导体装置中，提供将后一个节点的电位设定为预定电位的装置。 具体地说，提供了从前一个节点提供与后一个节点中存储的数据相对应的“1”或“0”的电位的装置。

公开(公告)号：US20150295570A1

公开(公告)日：2015-10-15

申请号：US14676923

申请日：2015-04-02

Applicant: Semiconductor Energy Laboratory Co., Ltd.

Inventor： Takuro OHMARU

IPC: H03K17/00 ,  H01L29/24 ,  H03K19/00 ,  H01L27/12

CPC classification number: G11C19/184 ,  G11C11/24 ,  G11C11/405 ,  G11C11/412 ,  G11C14/0063 ,  H01L27/1207 ,  H01L27/1225 ,  H01L29/24 ,  H01L29/7869 ,  H01L29/78696 ,  H03K3/356008 ,  H03K17/005 ,  H03K19/0016

Abstract: A holding circuit includes first to third input terminals, an output terminal, first to third switches, a capacitor, and a node. The first to third switches control conduction between the node and the first input terminal, conduction between the node and the output terminal, and conduction between the second input terminal and the output terminal, respectively. First and second terminals of the capacitor are electrically connected to the node and the third input terminal, respectively. The first to third switches are each a transistor comprising an oxide semiconductor layer comprising a semiconductor region. Owing to the structure, a potential change of the node in an electrically floating state can be suppressed; thus, the holding circuit can retain its state for a long time. The holding circuit can be used as a memory circuit for backup of a sequential circuit, for example.

Abstract translation: 保持电路包括第一至第三输入端子，输出端子，第一至第三开关，电容器和节点。 第一至第三开关控制节点与第一输入端之间的导通，节点与输出端之间的导通，以及第二输入端和输出端之间的导通。 电容器的第一和第二端子分别电连接到节点和第三输入端子。 第一至第三开关分别为包括半导体区域的氧化物半导体层的晶体管。 由于该结构，可以抑制电浮动状态下的节点的潜在变化; 因此，保持电路可以长时间保持其状态。 例如，保持电路可以用作用于备份时序电路的存储电路。

公开(公告)号：US20150213882A1

公开(公告)日：2015-07-30

申请号：US14679110

申请日：2015-04-06

Applicant: SEMICONDUCTOR ENERGY LABORATORY CO., LTD.

Inventor： Takuro OHMARU

IPC: G11C11/419 ,  G11C11/412 ,  G11C7/12

CPC classification number: G11C11/419 ,  G11C7/12 ,  G11C11/00 ,  G11C11/412

Abstract: To reduce power consumption, a memory circuit includes a latch unit in which first data and second data are rewritten and read in accordance with a control signal, a first switch unit that controls rewrite and read of the first data stored in the latch unit by being turned on or off in response to the control signal, and a second switch unit that controls rewrite and read of the second data stored in the latch unit by being turned on or off in response to the control signal. The latch unit includes a first inverter and a second inverter. At least one of the first inverter and the second inverter includes a first field-effect transistor, and a second field-effect transistor that has the same conductivity type as the first field-effect transistor and has a gate potential controlled in accordance with the control signal.

Abstract translation: 为了降低功耗，存储电路包括：锁存单元，其中根据控制信号重写和读取第一数据和第二数据;第一开关单元，其通过以下步骤控制对存储在锁存单元中的第一数据的重写和读取： 响应于所述控制信号而导通或断开;以及第二开关单元，其响应于所述控制信号而导通或关断控制存储在所述锁存单元中的所述第二数据的重写和读取。 闩锁单元包括第一反相器和第二反相器。 第一反相器和第二反相器中的至少一个包括第一场效应晶体管和第二场效应晶体管，其具有与第一场效应晶体管相同的导电类型，并且具有根据控制的栅极电位 信号。

公开(公告)号：US20140204645A1

公开(公告)日：2014-07-24

申请号：US14157574

申请日：2014-01-17

Applicant: SEMICONDUCTOR ENERGY LABORATORY CO., LTD.

Inventor： Takuro OHMARU ,  Naoaki TSUTSUI

IPC: G11C11/407

CPC classification number: G11C29/00 ,  G01R31/318597

Abstract: To supply a signal in which the occurrence of delays is prevented to a storage circuit. To provide a novel semiconductor device in which a load applied to a logic circuit is low. The following structure is completed: a storage circuit to which a plurality of data signals and a selection signal are supplied connects two combination circuits, and a storage circuit has a function of selecting one of a plurality of data signals in accordance with the selection signal. A selection circuit is not necessarily provided between the storage circuit and the combination circuit. As a result, the combination circuit can supply a signal in which the occurrence of delays is prevented to the storage circuit.

Abstract translation: 提供一种信号，其中阻止发生延迟到存储电路。 提供一种新颖的半导体器件，其中施加到逻辑电路的负载较低。 完成以下结构：提供多个数据信号和选择信号的存储电路连接两个组合电路，并且存储电路具有根据选择信号选择多个数据信号中的一个的功能。 在存储电路和组合电路之间不一定设置选择电路。 结果，组合电路可以向存储电路提供阻止发生延迟的信号。