公开(公告)号：US06376319B2

公开(公告)日：2002-04-23

申请号：US09972629

申请日：2001-10-09

申请人： Ting Cheong Ang ,  Shyue Fong Quek ,  Jun Song ,  Xing Yu

发明人： Ting Cheong Ang ,  Shyue Fong Quek ,  Jun Song ,  Xing Yu

IPC分类号： H01L21336

CPC分类号： H01L29/6653 ,  H01L29/66545 ,  H01L29/66553 ,  H01L29/6659 ,  H01L29/66628 ,  H01L29/7834

摘要： A process for fabricating a MOSFET device, featuring source/drain extension regions, formed after the utilization of high temperature processes, such as heavily doped source/drain regions, has been developed. Disposable insulator spacers are formed on the sides of doped, SEG silicon regions, followed formation of a gate insulator layer, and an overlying gate structure, on a region of the semiconductor substrate located between the doped SEG silicon regions. The temperature experienced during these process steps result in the formation of the heavily doped source/drain, underlying the SEG silicon regions. Selective removal of the disposable spacers, allows the source/drain extension regions to be placed in the space vacated by the disposable spacers, adjacent to the heavily doped source/drain region. Insulator spacers are then used to fill the spaces vacated by removal of the disposable spacers, directly overlying the source/drain extension regions. Additional iterations include the use of an L shaped spacer, overlying the source/drain extension region, as well as the formation of metal silicide, on the doped SEG silicon regions, and on the gate structures.

摘要翻译： 已经开发了一种用于制造MOSFET器件的方法，其特征在于在利用高温工艺（例如重掺杂源极/漏极区域）之后形成的源极/漏极延伸区域。 在掺杂的SEG硅区域的侧面上形成一次性绝缘体间隔物，随后在位于掺杂的SEG硅区域之间的半导体衬底的区域上形成栅极绝缘体层和覆盖栅极结构。 在这些工艺步骤中经历的温度导致SEG硅区域下方的重掺杂源极/漏极的形成。 选择性地去除一次性间隔件允许源极/漏极延伸区域被放置在与重掺杂的源极/漏极区域相邻的由一次性间隔物空出的空间中。 然后使用绝缘体间隔物来填充通过去除一次性间隔件而空出的空间，直接覆盖源极/漏极延伸区域。 另外的迭代包括在掺杂的SEG硅区域上以及栅极结构上使用覆盖源极/漏极延伸区域的L形间隔物以及金属硅化物的形成。

公开(公告)号：US06803314B2

公开(公告)日：2004-10-12

申请号：US09845480

申请日：2001-04-30

申请人： Shyue Fong Quek ,  Ting Cheong Ang ,  Yee Chong Wong ,  Sang Yee Long

发明人： Shyue Fong Quek ,  Ting Cheong Ang ,  Yee Chong Wong ,  Sang Yee Long

IPC分类号： H01L21302

CPC分类号： H01L21/76835 ,  H01L21/02115 ,  H01L21/02118 ,  H01L21/02131 ,  H01L21/02134 ,  H01L21/02137 ,  H01L21/022 ,  H01L21/3121 ,  H01L21/31629 ,  H01L21/31633 ,  H01L21/76807 ,  H01L21/76813

摘要： A double layered low dielectric constant material dual damascene metallization process is described. Metal lines are provided covered by an insulating layer overlying a semiconductor substrate. A first organic dielectric layer is deposited overlying the insulating layer. A second inorganic dielectric layer is deposited overlying the first dielectric layer. In a first method, a via pattern is etched into the second dielectric layer. The via pattern is etched into the first dielectric layer using the patterned second dielectric layer as a mask. Thereafter, a trench pattern is etched into the second inorganic dielectric layer to complete dual damascene openings. In a second method, a trench pattern is etched into the second dielectric layer. Thereafter, a via pattern is etched through the second inorganic dielectric layer and the first organic dielectric layer to complete dual damascene openings. In a third method, a via pattern is etched into the second dielectric layer. Then, simultaneously, the via pattern is etched into the first dielectric layer and a trench pattern is etched into the second inorganic dielectric layer to complete dual damascene openings in the fabrication of an integrated circuit device.

摘要翻译： 描述了双层低介电常数材料双镶嵌金属化工艺。 金属线被覆盖在半导体衬底上的绝缘层所覆盖。 沉积在绝缘层上的第一有机电介质层。 第二无机介电层沉积在第一介电层上。 在第一种方法中，通孔图案被蚀刻到第二介电层中。 使用图案化的第二介电层作为掩模将通孔图案蚀刻到第一介电层中。 此后，将沟槽图案蚀刻到第二无机介电层中以完成双镶嵌开口。 在第二种方法中，沟槽图案被蚀刻到第二介电层中。 此后，通过第二无机介电层和第一有机介电层蚀刻通孔图案以完成双镶嵌开口。 在第三种方法中，通孔图案被蚀刻到第二介电层中。 然后，同时，通孔图案被蚀刻到第一介电层中，并且沟槽图案被蚀刻到第二无机介电层中，以在集成电路器件的制造中完成双镶嵌开口。

公开(公告)号：US06492242B1

公开(公告)日：2002-12-10

申请号：US09609447

申请日：2000-07-03

申请人： Alex See ,  Cher Liang Randall Cha ,  Shyuz Fong Quek ,  Ting Cheong Ang ,  Wye Boon Loh ,  Sang Yee Loong ,  Jun Song ,  Chua Chee Tee

发明人： Alex See ,  Cher Liang Randall Cha ,  Shyuz Fong Quek ,  Ting Cheong Ang ,  Wye Boon Loh ,  Sang Yee Loong ,  Jun Song ,  Chua Chee Tee

IPC分类号： H01L2120

CPC分类号： H01L28/40 ,  H01L21/31683

摘要： A process for forming a high dielectric constant, (High K), layer, for a metal-oxide-metal, capacitor structure, featuring localized oxidation of an underlying metal layer, performed at a temperature higher than the temperature experienced by surrounding structures, has been developed. A first iteration of this process features the use of a laser ablation procedure, performed to a local region of an underlying metal layer, in an oxidizing ambient. The laser ablation procedure creates the desired, high temperature, only at the laser spot, allowing a high K layer to be created at this temperature, while the surrounding structures on a semiconductor substrate, not directly exposed to the laser ablation procedure remain at lower temperatures. A second iteration features the exposure of specific regions of an underlying metal layer, to a UV, or to an I line exposure procedure, performed in an oxidizing ambient, with the regions of an underlying metal layer exposed to the UV or I line procedure, via clear regions in an overlying photolithographic plate. This procedure also results in the formation of a high K layer, on a top portion of the underlying metal layer.

摘要翻译： 在高于周围结构所经历的温度的温度下进行的金属氧化物 - 金属电容器结构的高介电常数（高K）层，其特征在于底层金属层的局部氧化， 已经开发 该方法的第一次迭代的特征在于在氧化环境中使用对底层金属层的局部区域进行的激光烧蚀程序。 激光烧蚀过程仅在激光点产生所需的高温，允许在该温度下产生高K层，而不直接暴露于激光烧蚀过程的半导体衬底上的周围结构保持在较低温度 。 第二次迭代的特征在于在氧化环境中进行的底层金属层的特定区域到UV或I线曝光程序，暴露于UV或I线程序的下面的金属层的区域， 通过覆盖光刻板中的透明区域。 该过程还导致在下面的金属层的顶部上形成高K层。

公开(公告)号：US6143598A

公开(公告)日：2000-11-07

申请号：US246893

申请日：1999-02-08

申请人： John Elmslie Martin ,  Lap Chan ,  John Leonard Sudijono ,  Ting Cheong Ang

发明人： John Elmslie Martin ,  Lap Chan ,  John Leonard Sudijono ,  Ting Cheong Ang

IPC分类号： H01L21/02 ,  H01L21/314 ,  H01L21/316 ,  H01L21/8242

CPC分类号： H01L28/40 ,  H01L28/60 ,  H01L21/3144 ,  H01L21/31604 ,  H01L27/10852

摘要： A capacitor element of a semiconductor device used for high density semiconductor circuits is formed by the steps of forming the bottom plate of the capacitor, submitting the top of the bottom plate to plasma treatment in an oxidizing medium where nitrogen and oxygen are present, depositing a dielectric layer and submitting the top of the dielectric layer to plasma treatment in an oxidizing medium where nitrogen and oxygen are present. Various materials are used for the plasma treatment in an oxidizing medium where nitrogen and oxygen are present. While the present invention uses amorphous silicon as the dielectric material, plasma treatment in an oxidizing medium where nitrogen and oxygen are present can readily applied to a number of other dielectric materials. The objective in constructing capacitors for semiconductor circuits is to reduce the thickness of the dielectric material as much as possible and use a dielectric material for the dielectric which has a high dielectric constant, this increases the value of the capacitor electrical charge which can be carried by the capacitor. The objective of the present invention is to eliminate the leakage current between the plates of a capacitor so that the capacitor can maintain a high voltage between the top and the bottom plate.

摘要翻译： 用于高密度半导体电路的半导体器件的电容器元件是通过形成电容器的底板的步骤形成的，将底板的顶部在存在氮和氧的氧化介质中进行等离子体处理， 介电层，并将介电层的顶部在存在氮和氧的氧化介质中进行等离子体处理。 在存在氮和氧的氧化介质中使用各种材料进行等离子体处理。 虽然本发明使用非晶硅作为介电材料，但在存在氮和氧的氧化介质中的等离子体处理可以容易地应用于许多其它电介质材料。 用于半导体电路构造电容器的目的是尽可能地减小电介质材料的厚度，并且使用具有高介电常数的电介质的介电材料，这增加了电容器电荷的值 电容器。 本发明的目的是消除电容器板之间的漏电流，使得电容器能够在顶板和底板之间保持高电压。

公开(公告)号：US20070275538A1

公开(公告)日：2007-11-29

申请号：US11539612

申请日：2006-10-06

申请人： Ting Cheong Ang

发明人： Ting Cheong Ang

IPC分类号： H01L21/76

CPC分类号： H01L21/76224

摘要： A method of performing an STI gapfill process for semiconductor devices is provided. In a specific embodiment of the invention, the method includes forming an stop layer overlying a substrate. In addition, the method includes forming a trench within the substrate, with the trench having sidewalls, a bottom, and a depth. The method additionally includes forming a liner within the trench, the liner lining the sidewalls and bottom of the trench. Furthermore, the method includes filling the trench to a first depth with a first oxide. The first oxide is filled using a spin-on process. The method also includes performing a first densification process on the first oxide within the trench. In addition, the method includes depositing a second oxide within the trench using an HDP process to fill at least the entirety of the trench. The method also includes performing a second densification process on the first and second oxides within the trench.

摘要翻译： 提供了一种用于半导体器件的STI间隙填充处理的方法。 在本发明的具体实施方案中，该方法包括形成覆盖衬底的阻挡层。 此外，该方法包括在衬底内形成沟槽，其中沟槽具有侧壁，底部和深度。 该方法还包括在沟槽内形成衬垫，衬垫衬在沟槽的侧壁和底部。 此外，该方法包括用第一氧化物将沟槽填充到第一深度。 使用旋涂工艺填充第一氧化物。 该方法还包括对沟槽内的第一氧化物进行第一致密化处理。 另外，该方法包括使用HDP工艺在沟槽内沉积第二氧化物以填充至少整个沟槽。 该方法还包括对沟槽内的第一和第二氧化物进行第二致密化处理。

公开(公告)号：US06649517B2

公开(公告)日：2003-11-18

申请号：US09859353

申请日：2001-05-18

申请人： Young-Way Teh ,  Victor Seng Keong Lim ,  Ting Cheong Ang

发明人： Young-Way Teh ,  Victor Seng Keong Lim ,  Ting Cheong Ang

IPC分类号： H01L214763

CPC分类号： H01L23/5226 ,  H01L21/31116 ,  H01L21/31138 ,  H01L21/76804 ,  H01L23/5283 ,  H01L23/53228 ,  H01L23/53238 ,  H01L2924/0002 ,  H01L2924/00

摘要： A new method and structure is provided for the creation of interconnect lines. The cross section of the interconnect lines of the invention, taken in a plane that is perpendicular to the longitudinal direction of the interconnect lines, is a triangle as opposed to the conventional square or rectangular cross section of interconnect lines.

摘要翻译： 提供了一种新的方法和结构来创建互连线。 在与互连线的纵向方向垂直的平面中截取的本发明的互连线的横截面是与传统的互连线的矩形或矩形横截面相反的三角形。

公开(公告)号：US08110502B2

公开(公告)日：2012-02-07

申请号：US11394529

申请日：2006-03-30

申请人： Ting Cheong Ang

发明人： Ting Cheong Ang

IPC分类号： H01L21/4763 ,  H01L21/44

CPC分类号： H01L21/76843 ,  H01L21/76825 ,  H01L21/76831 ,  H01L21/7685 ,  H01L21/76862

摘要： A method for manufacturing a semiconductor device is provided. In a specific embodiment, the method includes providing a semiconductor substrate with a surface region. The surface region includes one or more layers overlying the semiconductor substrate. Additionally, the method includes forming a dielectric layer overlying the surface region and forming a diffusion barrier layer overlying the dielectric layer. Moreover, the method includes subjecting the diffusion barrier layer to a plasma environment to facilitate adhesion between the diffusion barrier layer and the dielectric layer at an interface region. Also, the method includes processing the semiconductor substrate while maintaining attachment between the dielectric layer and the diffusion barrier layer at the interface region. The subjecting the diffusion barrier layer to a plasma environment includes maintaining a thickness of the barrier diffusion layer.

摘要翻译： 提供一种制造半导体器件的方法。 在具体实施例中，该方法包括提供具有表面区域的半导体衬底。 表面区域包括覆盖半导体衬底的一个或多个层。 此外，该方法包括形成覆盖表面区域并形成覆盖在电介质层上的扩散阻挡层的电介质层。 此外，该方法包括使扩散阻挡层经受等离子体环境以促进在界面区域处的扩散阻挡层和电介质层之间的粘附。 此外，该方法包括处理半导体衬底，同时保持介电层和界面区域处的扩散阻挡层之间的附着。 将扩散阻挡层经受等离子体环境包括保持阻挡扩散层的厚度。

公开(公告)号：US08026151B2

公开(公告)日：2011-09-27

申请号：US12273323

申请日：2008-11-18

申请人： Ting Cheong Ang

发明人： Ting Cheong Ang

IPC分类号： H01L21/00

CPC分类号： H01L21/76224

摘要： A method of performing an STI gapfill process for semiconductor devices is provided. In a specific embodiment of the invention, the method includes forming an stop layer overlying a substrate. In addition, the method includes forming a trench within the substrate, with the trench having sidewalls, a bottom, and a depth. The method additionally includes forming a liner within the trench, the liner lining the sidewalls and bottom of the trench. Furthermore, the method includes filling the trench to a first depth with a first oxide. The first oxide is filled using a spin-on process. The method also includes performing a first densification process on the first oxide within the trench. In addition, the method includes depositing a second oxide within the trench using an HDP process to fill at least the entirety of the trench. The method also includes performing a second densification process on the first and second oxides within the trench.

摘要翻译： 提供了一种用于半导体器件的STI间隙填充处理的方法。 在本发明的具体实施方案中，该方法包括形成覆盖衬底的阻挡层。 此外，该方法包括在衬底内形成沟槽，其中沟槽具有侧壁，底部和深度。 该方法还包括在沟槽内形成衬垫，衬垫衬在沟槽的侧壁和底部。 此外，该方法包括用第一氧化物将沟槽填充到第一深度。 使用旋涂工艺填充第一氧化物。 该方法还包括对沟槽内的第一氧化物进行第一致密化处理。 另外，该方法包括使用HDP工艺在沟槽内沉积第二氧化物以填充至少整个沟槽。 该方法还包括对沟槽内的第一和第二氧化物进行第二致密化处理。

公开(公告)号：US07910475B2

公开(公告)日：2011-03-22

申请号：US12505414

申请日：2009-07-17

申请人： Ting Cheong Ang

发明人： Ting Cheong Ang

IPC分类号： H01L21/00

CPC分类号： H01L21/02131 ,  C23C16/30 ,  H01L21/02274 ,  H01L21/02362 ,  H01L21/31604 ,  H01L21/31629 ,  H01L21/31633 ,  H01L21/7684 ,  H01L23/5329 ,  H01L2924/0002 ,  H01L2924/00

摘要： A method for forming a semiconductor device is provided. In one embodiment, the method includes providing a semiconductor substrate with a surface region. The surface region includes one or more layers overlying the semiconductor substrate. In addition, the method includes depositing a dielectric layer overlying the surface region. The dielectric layer is formed by a CVD process. Furthermore, the method includes forming a diffusion barrier layer overlying the dielectric layer. In addition, the method includes forming a conductive layer overlying the diffusion barrier layer. Additionally, the method includes reducing the thickness of the conductive layer using a chemical-mechanical polishing process. The CVD process utilizes fluorine as a reactant to form the dielectric layer. In addition, the dielectric layer is associated with a dielectric constant equal or less than 3.3.

摘要翻译： 提供一种形成半导体器件的方法。 在一个实施例中，该方法包括提供具有表面区域的半导体衬底。 表面区域包括覆盖半导体衬底的一个或多个层。 此外，该方法包括沉积覆盖表面区域的介电层。 介电层通过CVD工艺形成。 此外，该方法包括形成覆盖在电介质层上的扩散阻挡层。 此外，该方法包括形成覆盖扩散阻挡层的导电层。 另外，该方法包括使用化学机械抛光工艺来减小导电层的厚度。 CVD工艺利用氟作为反应物形成电介质层。 此外，介电层与等于或小于3.3的介电常数相关联。

公开(公告)号：US20100006975A1

公开(公告)日：2010-01-14

申请号：US12258366

申请日：2008-10-24

申请人： Ting Cheong Ang

发明人： Ting Cheong Ang

IPC分类号： H01L29/00 ,  H01L21/76

CPC分类号： H01L21/76224

摘要： A method of forming a semiconductor structure is provided. The method includes providing a semiconductor substrate with a substrate region. The method also includes forming a pad oxide layer overlying the substrate region. The method additionally includes forming a stop layer overlying the pad oxide layer. Furthermore, the method includes patterning the stop layer and the pad oxide layer to expose a portion of the substrate region. In addition, the method includes forming a trench within an exposed portion of the substrate region, the trench having sidewalls and a bottom and a height. Also, the method includes depositing alternating layers of oxide and silicon nitride to at least fill the trench, the oxide being deposited by an HDP-CVD process. The method additionally includes performing a planarization process to remove a portion of the silicon nitride and oxide layers. In addition, the method includes removing the pad oxide and stop layers.

摘要翻译： 提供一种形成半导体结构的方法。 该方法包括提供具有衬底区域的半导体衬底。 该方法还包括形成覆盖衬底区域的衬垫氧化物层。 该方法还包括形成覆盖衬垫氧化物层的阻挡层。 此外，该方法包括图案化停止层和衬垫氧化物层以暴露衬底区域的一部分。 此外，该方法包括在衬底区域的暴露部分内形成沟槽，沟槽具有侧壁，底部和高度。 此外，该方法包括沉积氧化物和氮化硅的交替层以至少填充沟槽，氧化物通过HDP-CVD工艺沉积。 该方法另外包括执行平坦化处理以去除一部分氮化硅和氧化物层。 此外，该方法包括去除衬垫氧化物并停止层。