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    Array of three-gate flash memory cells with individual memory cell read, program and erase
    33.
    发明授权
    Array of three-gate flash memory cells with individual memory cell read, program and erase 有权

    公开(公告)号：US10460811B2

    公开(公告)日：2019-10-29

    申请号：US16387377

    申请日：2019-04-17

    Applicant: Silicon Storage Technology, Inc.

    Inventor： Hieu Van Tran ,  Vipin Tiwari ,  Nhan Do

    IPC: G11C11/34 ,  G11C16/14 ,  G11C16/10 ,  G11C16/04

    Abstract: A memory device and method of erasing same that includes a substrate of semiconductor material and a plurality of memory cells formed on the substrate and arranged in an array of rows and columns. Each of the memory cells includes spaced apart source and drain regions in the substrate, with a channel region in the substrate extending there between, a floating gate disposed over and insulated from a first portion of the channel region which is adjacent the source region, a select gate disposed over and insulated from a second portion of the channel region which is adjacent the drain region, and a program-erase gate disposed over and insulated from the source region. The program-erase gate lines alone or in combination with the select gate lines, or the source lines, are arranged in the column direction so that each memory cell can be individually programmed, read and erased.

    System And Method For Storing And Retrieving Multibit Data In Non-volatile Memory Using Current Multipliers
    34.
    发明申请
    System And Method For Storing And Retrieving Multibit Data In Non-volatile Memory Using Current Multipliers 审中-公开

    公开(公告)号：US20190206486A1

    公开(公告)日：2019-07-04

    申请号：US16213860

    申请日：2018-12-07

    Applicant: Silicon Storage Technology, Inc.

    Inventor： Vipin Tiwari ,  Hieu Van Tran ,  Nhan Do

    IPC: G11C11/56

    CPC classification number: G11C11/5642 ,  G11C2211/5641

    Abstract: A memory device includes memory cells each configured to produce an output current during a read operation. Circuitry is configured to, for each of the memory cells, generate a read value based on the output current of the memory cell. Circuitry is configured to, for each of the memory cells, multiply the read value for the memory cell by a multiplier to generate a multiplied read value, wherein the multiplier for each of the memory cells is different from the multipliers for any others of the memory cells. Circuitry is configured to sum the multiplied read values. The read values can be electrical currents, electrical voltages or numerical values. Alternatively, added constant values can be used instead of multipliers. The multipliers or constants can be applied to read currents from individual cells, or read currents on entire bit lines.

    System And Method For Implementing Configurable Convoluted Neural Networks With Flash Memories
    37.
    发明申请
    System And Method For Implementing Configurable Convoluted Neural Networks With Flash Memories 审中-公开

    公开(公告)号：US20190088329A1

    公开(公告)日：2019-03-21

    申请号：US16107282

    申请日：2018-08-21

    Applicant: Silicon Storage Technology, Inc

    Inventor： Vipin Tiwari ,  Nhan Do

    IPC: G11C16/04 ,  H01L27/11521 ,  G06N3/06

    Abstract: A memory array with memory cells arranged in rows and columns. Each memory cell includes source and drain regions with a channel region there between, a floating gate disposed over a first channel region portion, and a second gate disposed over a second channel region portion. A plurality of bit lines each extends along one of the columns and is electrically connected to the drain regions of a first group of one or more of the memory cells in the column and is electrically isolated from the drain regions of a second group of one or more of the memory cells in the column. A plurality of source lines each is electrically connected to the source regions memory cells in one of the columns or rows. A plurality of gate lines each is electrically connected to the second gates of memory cells in one of the columns or rows.

    Method of forming pairs of three-gate non-volatile flash memory cells using two polysilicon deposition steps
    38.
    发明授权
    Method of forming pairs of three-gate non-volatile flash memory cells using two polysilicon deposition steps 有权

    公开(公告)号：US10217850B2

    公开(公告)日：2019-02-26

    申请号：US15474879

    申请日：2017-03-30

    Applicant: Silicon Storage Technology, Inc.

    Inventor： Feng Zhou ,  Xian Liu ,  Chien-Sheng Su ,  Nhan Do ,  Chunming Wang

    IPC: H01L29/66 ,  H01L29/788 ,  H01L27/07 ,  H01L29/08 ,  H01L29/423 ,  H01L21/28

    Abstract: A simplified method for forming pairs of non-volatile memory cells using two polysilicon depositions. A first polysilicon layer is formed on and insulated from the semiconductor substrate in a first polysilicon deposition process. A pair of spaced apart insulation blocks are formed on the first polysilicon layer. Exposed portions of the first poly silicon layer are removed while maintaining a pair of polysilicon blocks of the first polysilicon layer each disposed under one of the pair of insulation blocks. A second polysilicon layer is formed over the substrate and the pair of insulation blocks in a second polysilicon deposition process. Portions of the second polysilicon layer are removed while maintaining a first polysilicon block (disposed between the pair of insulation blocks), a second polysilicon block (disposed adjacent an outer side of one insulation block), and a third polysilicon block (disposed adjacent an outer side of the other insulation block).

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