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    Techniques for phase tuning for process optimization
    31.
    发明授权
    Techniques for phase tuning for process optimization 有权
    用于过程优化的相位调整技术

    公开(公告)号：US08959465B2

    公开(公告)日：2015-02-17

    申请号：US13997565

    申请日：2011-12-30

    Applicant: Paul A. Nyhus ,  Shem O. Ogadhoh ,  Swaminathan Sivakumar ,  Seongtae Jeong

    Inventor： Paul A. Nyhus ,  Shem O. Ogadhoh ,  Swaminathan Sivakumar ,  Seongtae Jeong

    IPC: G06F17/50 ,  G03F1/36 ,  G03F1/70

    CPC classification number: G06F17/5009 ,  G03F1/36 ,  G03F1/70 ,  G06F17/5068

    Abstract: Techniques are provided for determining how thick or how deep to make the phased regions of a lithography mask. One example embodiment provides a method that includes: providing a first mask layout design including a first test set, and providing a second mask layout design including a second test set, wherein the second test set is larger than the first test set; simulating critical dimensions through focus of structures of interest in the first test set for a range of phase depths/thicknesses, and selecting an initial preferred mask phase depth/thickness based on results of the simulating; and generating a fast thick-mask model (FTM) at the initial preferred phase depth/thickness, and correcting the second test set of the second mask layout design using the FTM, thereby providing an optimized mask layout design. A mask having the optimized mask layout design may be implemented to give the optimum patterning.

    Abstract translation: 提供了用于确定制造光刻掩模的相位区域的厚度或深度的技术。 一个示例性实施例提供了一种方法，其包括：提供包括第一测试集的第一掩模布局设计，以及提供包括第二测试集的第二掩模布局设计，其中所述第二测试集大于所述第一测试集; 通过针对一系列相位深度/厚度的第一测试集合中关注的结构的焦点来模拟关键尺寸，并且基于模拟结果选择初始优选的掩模相位深度/厚度; 并且以最初的优选相位深度/厚度生成快速厚掩模模型（FTM），并且使用FTM校正第二掩模布局设计的第二测试集，由此提供优化的掩模布局设计。 可以实施具有优化的掩模布局设计的掩模以给出最佳图案化。

    Spacer assisted pitch division lithography
    32.
    发明授权
    Spacer assisted pitch division lithography 有权
    间隔辅助间距光刻

    公开(公告)号：US08860184B2

    公开(公告)日：2014-10-14

    申请号：US13976077

    申请日：2011-12-29

    Applicant: Swaminathan Sivakumar ,  Elliot N. Tan

    Inventor： Swaminathan Sivakumar ,  Elliot N. Tan

    IPC: H01L29/06 ,  H01L23/58 ,  H01L21/44 ,  H01L21/02

    CPC classification number: H01L21/02587 ,  H01L21/02658 ,  H01L21/0337 ,  H01L21/28 ,  H01L21/76816 ,  H01L29/0684 ,  Y10S438/942

    Abstract: Spacer-based pitch division lithography techniques are disclosed that realize pitches with both variable line widths and variable space widths, using a single spacer deposition. The resulting feature pitches can be at or below the resolution limit of the exposure system being used, but they need not be, and may be further reduced (e.g., halved) as many times as desired with subsequent spacer formation and pattern transfer processes as described herein. Such spacer-based pitch division techniques can be used, for instance, to define narrow conductive runs, metal gates and other such small features at a pitch smaller than the original backbone pattern.

    Abstract translation: 公开了使用单个间隔物沉积来实现具有可变线宽度和可变空间宽度的间距的基于间隔物的间距光刻技术。 所得到的特征间距可以处于或低于所使用的曝光系统的分辨率极限，但是它们不需要并且可以进一步减少（例如，减半），如所需的随后的间隔物形成和图案转移过程所需的多次 这里。 这种基于间隔物的螺距分割技术可以用于例如以比原始骨架图案小的间距来限定窄导电线，金属栅极和其它这样的小特征。

    Transistor having raised source/drain self-aligned contacts and method of forming same
    33.
    发明授权
    Transistor having raised source/drain self-aligned contacts and method of forming same 有权
    具有升高的源极/漏极自对准触点的晶体管及其形成方法

    公开(公告)号：US08013426B2

    公开(公告)日：2011-09-06

    申请号：US11965850

    申请日：2007-12-28

    Applicant: Swaminathan Sivakumar

    Inventor： Swaminathan Sivakumar

    IPC: H01L29/72

    CPC classification number: H01L21/76897 ,  H01L29/66628 ,  H01L29/66659

    Abstract: A transistor structure and a method of forming same. The transistor structure includes: a semiconductor substrate having a gate-side surface; a gate disposed on the gate-side surface, the gate extending above the gate-side surface by a first height; a semiconductor extension disposed on the gate-side surface and extending above the gate-side surface by a second height larger than the first height, the semiconductor extension including a diffusion region having a diffusion surface located at the second height; and a diffusion contact element electrically coupled to the diffusion surface.

    Abstract translation: 晶体管结构及其形成方法。 晶体管结构包括：具有栅极侧表面的半导体衬底; 设置在所述栅极侧表面上的栅极，所述栅极在所述栅极侧表面上延伸第一高度; 半导体延伸部，其设置在所述栅极侧表面上并且在所述栅极侧表面上方延伸高于所述第一高度的第二高度，所述半导体延伸部包括具有位于所述第二高度的扩散表面的扩散区域; 以及电耦合到扩散表面的扩散接触元件。

    Double patterning techniques and structures
    34.
    发明授权
    Double patterning techniques and structures 有权
    双重图案化技术和结构

    公开(公告)号：US07915171B2

    公开(公告)日：2011-03-29

    申请号：US12111702

    申请日：2008-04-29

    Applicant: Charles H. Wallace ,  Matthew Tingey ,  Swaminathan Sivakumar

    Inventor： Charles H. Wallace ,  Matthew Tingey ,  Swaminathan Sivakumar

    IPC: H01L21/306 ,  G03F1/00

    CPC classification number: H01L21/308 ,  H01L21/0271 ,  H01L21/3086 ,  H01L21/3088

    Abstract: Double patterning techniques and structures are generally described. In one example, a method includes depositing a first photoresist to a semiconductor substrate, forming a first integrated circuit (IC) pattern in the first photoresist, the first IC pattern comprising one or more trench structures, protecting the first IC pattern in the first photoresist from actions that form a second IC pattern in a second photoresist, depositing the second photoresist to the first IC pattern, and forming the second IC pattern in the second photoresist, the second IC pattern comprising one or more structures that are sufficiently close to the one or more trench structures of the first IC pattern to cause scumming of the second photoresist in the one or more trench structures of the first IC pattern.

    Abstract translation: 通常描述双重图案形成技术和结构。 在一个实例中，一种方法包括将第一光致抗蚀剂沉积到半导体衬底，在第一光致抗蚀剂中形成第一集成电路（IC）图案，第一IC图案包括一个或多个沟槽结构，保护第一光致抗蚀剂 从在第二光致抗蚀剂中形成第二IC图案的动作，将第二光致抗蚀剂沉积到第一IC图案，以及在第二光致抗蚀剂中形成第二IC图案，第二IC图案包括一个或多个足够接近该一个的结构 或更多个沟槽结构，以使第一IC图案的一个或多个沟槽结构中的第二光致抗蚀剂浮渣。

    Negative tone double patterning method
    35.
    发明授权
    Negative tone double patterning method 有权
    负色双重图案化方法

    公开(公告)号：US07820550B2

    公开(公告)日：2010-10-26

    申请号：US12205744

    申请日：2008-09-05

    Applicant: Paul Nyhus ,  Charles Wallace ,  Swaminathan Sivakumar

    Inventor： Paul Nyhus ,  Charles Wallace ,  Swaminathan Sivakumar

    IPC: H01L21/311

    CPC classification number: G03F7/0035 ,  Y10T428/24802

    Abstract: A method of forming a pattern on a wafer is provided. The method includes applying a photoresist on the wafer and exposing the wafer to define a first pattern on the photoresist. The method also includes exposing the wafer to define a second pattern on the photoresist, wherein each of the first and second patterns comprises unexposed portions of the photoresist and developing the wafer to form the first and second patterns on the photoresist, wherein the first and second patterns are formed by removing the unexposed portions of the photoresist.

    Abstract translation: 提供了在晶片上形成图案的方法。 该方法包括在晶片上施加光致抗蚀剂并暴露晶片以在光致抗蚀剂上限定第一图案。 该方法还包括曝光晶片以限定光致抗蚀剂上的第二图案，其中第一和第二图案中的每一个包括光致抗蚀剂的未曝光部分，并且显影晶片以在光致抗蚀剂上形成第一和第二图案，其中第一和第二图案 通过去除光致抗蚀剂的未曝光部分形成图案。

    Cross-shaped sub-resolution assist feature
    40.
    发明授权
    Cross-shaped sub-resolution assist feature 失效
    十字形分解辅助功能

    公开(公告)号：US07521157B2

    公开(公告)日：2009-04-21

    申请号：US11351084

    申请日：2006-02-09

    Applicant: Charles H. Wallace ,  Swaminathan Sivakumar ,  Shannon E. Daviess

    Inventor： Charles H. Wallace ,  Swaminathan Sivakumar ,  Shannon E. Daviess

    IPC: G03F1/00

    CPC classification number: G03F1/36

    Abstract: Cross-shaped sub-resolution assist features may be utilized to print lithographic patterns in semiconductor fabrication processes. The crosses may be isolated structures or may be part of a grid arrangement. The main features, such as contacts, may be positioned on the mask so as to be intersected by the cross-shaped sub-resolution assist features. In some embodiments, the cross-shaped sub-resolution assist features may intersect the main feature at its center point in both the x and y directions.

    Abstract translation: 在半导体制造工艺中可以使用十字形分解辅助特征来印刷平版印刷图案。 十字架可以是隔离结构，也可以是网格布置的一部分。 诸如触点的主要特征可以位于掩模上，以便与十字形分解辅助特征相交。 在一些实施例中，十字形辅助分辨率辅助特征可以在x和y方向的中心点处与主要特征相交。

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