公开(公告)号：US09666253B2

公开(公告)日：2017-05-30

申请号：US14924069

申请日：2015-10-27

Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY LTD.

Inventor： Jonathan Tsung-Yung Chang ,  Chiting Cheng ,  Cheng Hung Lee ,  Hung-Jen Liao ,  Michael Clinton

IPC: G11C7/12 ,  G11C5/14 ,  G11C7/10 ,  G11C7/06 ,  G11C7/22 ,  G11C8/10 ,  G11C8/06 ,  G11C8/08

CPC classification number: G11C7/12 ,  G11C5/14 ,  G11C5/147 ,  G11C7/06 ,  G11C7/065 ,  G11C7/10 ,  G11C7/22 ,  G11C8/06 ,  G11C8/08 ,  G11C8/10 ,  G11C11/417 ,  G11C11/418

Abstract: A dual rail memory operable at a first voltage and a second voltage, the dual rail memory includes: a memory array operates at the first voltage; a word line driver circuit configured to drive a word line of the memory array to the first voltage; a data path configured to transmit an input data signal or an output data signal; and a control circuit configured to generate control signals to the memory array, the word line driver circuit and the data path; wherein the data path and the control circuit are configured to operate at both the first and second voltages. Associated memory macro and method are also disclosed.

公开(公告)号：US09589885B2

公开(公告)日：2017-03-07

申请号：US14835788

申请日：2015-08-26

Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.

Inventor： Hung-Jen Liao ,  Jung-Hsuan Chen ,  Chien Chi Tien ,  Ching-Wei Wu ,  Jui-Che Tsai ,  Hong-Chen Cheng ,  Chung-Hsing Wang

IPC: H01L23/00 ,  H01L23/50 ,  H01L27/11 ,  H01L23/532 ,  H01L27/02 ,  H01L23/528 ,  H01L23/498 ,  H01L23/522

CPC classification number: H01L23/50 ,  H01L23/49811 ,  H01L23/49827 ,  H01L23/5226 ,  H01L23/528 ,  H01L23/53204 ,  H01L27/0203 ,  H01L27/11 ,  H01L2924/0002 ,  H01L2924/00

Abstract: An integrated circuit (IC) memory device includes a first conductive layer. The IC memory device also includes a second conductive layer over the first conductive layer. The IC memory device further includes a first-type pin box electrically coupled with the first conductive layer. The IC memory device additionally includes a second-type pin box, different from the first-type pin box, electrically coupled with the second conductive layer.

Abstract translation: 集成电路（IC）存储器件包括第一导电层。 IC存储器件还包括在第一导电层上的第二导电层。 IC存储器件还包括与第一导电层电耦合的第一型引脚盒。 IC存储器件还包括与第一类型引脚盒不同的第二型引脚盒，与第二导电层电耦合。

公开(公告)号：US09425095B2

公开(公告)日：2016-08-23

申请号：US14720824

申请日：2015-05-24

Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.

Inventor： You-Cheng Xiao ,  Yen-Huei Chen ,  Jung-Hsuan Chen ,  Shao-Yu Chou ,  Li-Chun Tien ,  Hung-Jen Liao

IPC: H01L21/768 ,  H01L23/528 ,  H01L23/482 ,  H01L23/485 ,  H01L23/522

CPC classification number: H01L21/76879 ,  H01L21/768 ,  H01L21/76832 ,  H01L23/4824 ,  H01L23/485 ,  H01L23/522 ,  H01L23/528 ,  H01L23/5286 ,  H01L2924/0002 ,  H01L2924/00

Abstract: A system and method for a distributed metal routing is disclosed. An embodiment comprises a metal_0 layer with a metal_1 layer overlying the metal_0 layer. The metal_1 layer comprises separate parallel lines, with lines having different signals being distributed across the metal_1 layer. Such a layout decreases the parasitic resistance within the metal_0 layer as it decreases the distance current travels. Additionally, the distributed layout in metal_1 allows connections to be made to a metal_2 layer without the need for a hammer head connection of vias.

公开(公告)号：US09418729B2

公开(公告)日：2016-08-16

申请号：US15007894

申请日：2016-01-27

Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.

Inventor： Hidehiro Fujiwara ,  Kao-Cheng Lin ,  Yen-Huei Chen ,  Hung-Jen Liao

IPC: G11C7/10 ,  G11C11/417 ,  G11C5/02 ,  G11C5/06

CPC classification number: G11C11/419 ,  G11C5/02 ,  G11C5/06 ,  G11C7/1051 ,  G11C7/1057 ,  G11C7/106 ,  G11C7/1078 ,  G11C7/22 ,  G11C8/14 ,  G11C8/16 ,  G11C11/417 ,  H01L23/535 ,  H01L27/1104

Abstract: A circuit includes a first data line, a second data line, a reference node, and a memory cell. The memory cell includes a data node, a first transistor, a second transistor, and a third transistor. The first transistor and the second transistor are connected in series between the first data line and the reference node. The first transistor is configured to be turned off when the gate of the first transistor has a voltage level corresponding to the first logical value. The third transistor is between the data node and the second data line. The third transistor is configured to be turned off when a gate of the third transistor has a voltage level corresponding to a second logical value different from the first logical value.

Abstract translation: 电路包括第一数据线，第二数据线，参考节点和存储器单元。 存储单元包括数据节点，第一晶体管，第二晶体管和第三晶体管。 第一晶体管和第二晶体管串联连接在第一数据线和参考节点之间。 当第一晶体管的栅极具有与第一逻辑值对应的电压电平时，第一晶体管被配置为截止。 第三晶体管位于数据节点和第二数据线之间。 当第三晶体管的栅极具有与不同于第一逻辑值的第二逻辑值相对应的电压电平时，第三晶体管被配置为截止。

公开(公告)号：US09129956B2

公开(公告)日：2015-09-08

申请号：US14102623

申请日：2013-12-11

Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.

Inventor： Hung-Jen Liao ,  Jung-Hsuan Chen ,  Chien Chi Tien ,  Ching-Wei Wu ,  Jui-Che Tsai ,  Hong-Chen Cheng ,  Chung-Hsing Wang

IPC: H01L23/00 ,  H01L23/498 ,  H01L27/11 ,  H01L23/532 ,  H01L27/02 ,  H01L23/528

CPC classification number: H01L23/50 ,  H01L23/49811 ,  H01L23/49827 ,  H01L23/5226 ,  H01L23/528 ,  H01L23/53204 ,  H01L27/0203 ,  H01L27/11 ,  H01L2924/0002 ,  H01L2924/00

Abstract: An integrated circuit (IC) memory device that includes a first conductive layer, a second conductive layer electrically coupled to the first conductive layer, the second conductive layer formed over the first conductive layer, a third conductive layer separated from the second conductive layer, the third conductive layer formed over the second conductive layer, a fourth conductive layer electrically coupled to the third conductive layer, the fourth conductive layer formed over the third conductive layer, a 2P2E pin box formed in and electrically coupled to the first conductive layer or the second conductive layer and a 1P1E pin box formed in and electrically coupled to the third conductive layer or the fourth conductive layer.

Abstract translation: 一种集成电路（IC）存储器件，其包括第一导电层，电耦合到第一导电层的第二导电层，形成在第一导电层上的第二导电层，与第二导电层分离的第三导电层， 形成在所述第二导电层上的第三导电层，电耦合到所述第三导电层的第四导电层，形成在所述第三导电层上的所述第四导电层，形成在所述第一导电层中或与所述第二导电层电连接的第二导电层， 导电层和形成在第三导电层或第四导电层中并电耦合到第三导电层的1P1E引脚盒。

公开(公告)号：US12183428B2

公开(公告)日：2024-12-31

申请号：US18358177

申请日：2023-07-25

Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD. ,  TSMC CHINA COMPANY, LIMITED

Inventor： Yi-Tzu Chen ,  Ching-Wei Wu ,  Hau-Tai Shieh ,  Hung-Jen Liao ,  Fu-An Wu ,  He-Zhou Wan ,  XiuLi Yang

IPC: G11C7/12 ,  G11C7/10 ,  G11C7/14 ,  G11C7/22

Abstract: A memory circuit includes a NAND logic gate configured to receive a first bit line signal and a second bit line signal, and to generate a first signal. The memory circuit further includes a first P-type transistor coupled to the NAND logic gate, and configured to receive a first clock signal. The memory circuit further includes a first N-type transistor coupled to the NAND logic gate, and configured to receive a first pre-charge signal. The memory circuit further includes a first latch coupled to the NAND logic gate, and configured to latch the first signal in response to at least the first clock signal or the first pre-charge signal.

公开(公告)号：US20240055048A1

公开(公告)日：2024-02-15

申请号：US18362736

申请日：2023-07-31

Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.

Inventor： Mahmut Sinangil ,  Yen-Huei Chen ,  Yen-Ting Lin ,  Hung-Jen Liao ,  Jonathan Tsung-Yung Chang

IPC: G11C11/419 ,  G11C11/418

CPC classification number: G11C11/419 ,  G11C11/418

Abstract: A twelve-transistor (12T) memory cell for a memory device that includes a transmission gate, a cross-coupled inverter circuit operably connected to the transmission gate, and a tri-state inverter operably connected to the cross-coupled inverter circuit. The cross-coupled inverter includes another tri-state inverter cross-coupled to an inverter circuit. Various operations for the 12T memory cell, as well as circuitry to perform the operations, are disclosed.

公开(公告)号：US11854970B2

公开(公告)日：2023-12-26

申请号：US17816108

申请日：2022-07-29

Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.

Inventor： Chien-Yuan Chen ,  Cheng-Hung Lee ,  Hung-Jen Liao ,  Hau-Tai Shieh ,  Kao-Cheng Lin ,  Wei-Min Chan

IPC: H01L23/528 ,  H01L27/092 ,  G06F30/392 ,  H01L21/8238 ,  H10B10/00

CPC classification number: H01L23/528 ,  G06F30/392 ,  H01L21/823807 ,  H01L21/823814 ,  H01L21/823871 ,  H01L21/823878 ,  H01L27/092 ,  H10B10/12

Abstract: Circuit devices, such as integrated circuit devices, are constructed with combination circuits that include two or more cascading transistors, and one or more metal layers disposed over the cascading transistors. The cascading transistors include multiple internal nodes (e.g., common source/drain regions). The multiple internal nodes are not connected to a common metal stripe (the same metal stripe) in the one or more metal layers. The absence of the connections between the internal nodes and a common metal stripe reduce or eliminate the load on the internal nodes. The transistors in the cascading transistors are independent of each other.

公开(公告)号：US20230386567A1

公开(公告)日：2023-11-30

申请号：US18446072

申请日：2023-08-08

Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.

Inventor： Chien-Yuan Chen ,  Hau-Tai Shieh ,  Cheng Hung Lee ,  Hung-Jen Liao

IPC: G11C11/419 ,  G11C11/412

CPC classification number: G11C11/419 ,  G11C11/412

Abstract: A memory device and a method of operating the same are disclosed. In one aspect, the memory device includes a plurality of memory arrays and a controller including a plurality of buffers including a first buffer connected to a first memory array and a second buffer connected to a second memory array. The first and second memory arrays are disposed on opposing sides of the controller. The memory device can include a first wire extending in a first direction and connected to the first buffer, a second wire extending in the first direction and connected to the second buffer, and a third wire connected to the first and second wires and extending in a second direction that is substantially perpendicular to the first direction. The third wire can be electrically connected to the controller, and respective lengths of the first wire and the second wire are substantially the same.

公开(公告)号：US11830543B2

公开(公告)日：2023-11-28

申请号：US17808536

申请日：2022-06-23

Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.

Inventor： Yen-Huei Chen ,  Hidehiro Fujiwara ,  Hung-Jen Liao ,  Jonathan Tsung-Yung Chang

IPC: G11C11/419 ,  G11C11/412 ,  G06N3/08 ,  G06F17/16 ,  G11C11/418

CPC classification number: G11C11/419 ,  G06F17/16 ,  G06N3/08 ,  G11C11/412 ,  G11C11/418

Abstract: A memory circuit includes a first memory array including first memory cells wherein a plurality of first word lines is coupled with a plurality of rows of first memory cells in a first segment of the first memory array, and a plurality of second word lines is coupled with the plurality of rows of first memory cells in a second segment of the first memory array. The memory circuit also includes a read circuit configured to retrieve data from the first memory cells of the first memory array and a computation circuit configured to perform a matrix computation by combining first data retrieved from the first memory cells of the first segment with second data retrieved from the first memory cells of the second segment.