公开(公告)号：US20140111301A1

公开(公告)日：2014-04-24

申请号：US13655419

申请日：2012-10-18

Applicant: TEXAS INSTRUMENTS INCORPORATED

Inventor： Byron Lovell Williams ,  John Britton Robbins

IPC: H01C1/012 ,  H01L21/02

CPC classification number: H01C7/006 ,  H01C7/06 ,  H01C17/075 ,  H01L23/5228 ,  H01L23/5258 ,  H01L23/647 ,  H01L27/0802 ,  H01L28/24 ,  H01L2924/0002 ,  H01L2924/00

Abstract: The resistance of a thin-film resistor is substantially increased by forming the thin-film resistor to line one or more non-conductive trenches. By lining the one or more non-conductive trenches, the overall length of the resistor is increased while still consuming approximately the same surface area as a conventional resistor.

Abstract translation: 薄膜电阻器的电阻通过将薄膜电阻器形成为一个或多个非导电沟槽线来实质上增加。 通过衬套一个或多个非导电沟槽，电阻器的总长度增加，同时仍然消耗与常规电阻器大致相同的表面积。

公开(公告)号：US11973052B2

公开(公告)日：2024-04-30

申请号：US17242380

申请日：2021-04-28

Applicant: Texas Instruments Incorporated

Inventor： Chien-Chang Li ,  Hung-Yu Chou ,  Sheng-Wen Huang ,  Zi-Xian Zhan ,  Byron Lovell Williams

IPC: H01L23/00 ,  H01L21/48 ,  H01L21/56 ,  H01L23/31 ,  H01L23/495

CPC classification number: H01L24/48 ,  H01L21/4825 ,  H01L21/565 ,  H01L23/3107 ,  H01L23/49513 ,  H01L23/4952 ,  H01L23/49575 ,  H01L24/85 ,  H01L2224/48137 ,  H01L2224/48245 ,  H01L2224/48465 ,  H01L2224/48479 ,  H01L2224/85051 ,  H01L2224/85205

Abstract: An electronic device includes a bond wire with a first end bonded by a ball bond to a planar side of a first conductive plate, and a second end bonded by a stitch bond to a conductive stud bump at an angle greater than or equal to 60 degrees. A wirebonding method includes bonding the first end of the conductive bond wire to the first conductive plate includes forming a ball bond to join the first end of the conductive bond wire to a planar side of the first conductive plate by a ball bond, and bonding the second end of the conductive bond wire to the conductive stud bump includes forming a stitch bond to join the second end of the conductive bond wire to the conductive stud bump.

公开(公告)号：US20240120367A1

公开(公告)日：2024-04-11

申请号：US18390395

申请日：2023-12-20

Applicant: Texas Instruments Incorporated

Inventor： Elizabeth Costner Stewart ,  Thomas Dyer Bonifield ,  Jeffrey Alan West ,  Byron Lovell Williams

IPC: H01G4/30 ,  H01L23/00 ,  H01L23/495 ,  H01L25/16

CPC classification number: H01L28/60 ,  H01L23/49575 ,  H01L24/05 ,  H01L25/16 ,  H01L2224/0556 ,  H01L2224/05624

Abstract: An electronic device includes a first dielectric layer above a semiconductor layer, lower-bandgap dielectric layer above the first dielectric layer, the lower-bandgap dielectric layer having a bandgap energy less than a bandgap energy of the first dielectric layer, a first capacitor plate above the lower-bandgap dielectric layer in a first plane of first and second directions, a second dielectric layer above the first capacitor plate, a second capacitor plate above the second dielectric layer in a second plane of the first and second directions, the first and second capacitor plates spaced apart from one another along a third direction, and a conductive third capacitor plate above the second dielectric layer in the second plane, the third capacitor plate spaced apart from the second capacitor plate in the second plane.

公开(公告)号：US20240113095A1

公开(公告)日：2024-04-04

申请号：US18067703

申请日：2022-12-17

Applicant: Texas Instruments Incorporated

Inventor： Yoshihiro Takei ,  Mitsuhiro Sugimoto ,  Byron Lovell Williams ,  Jeffrey Alan West

IPC: H01L27/01 ,  H01L21/02 ,  H01L23/00 ,  H01L23/31

CPC classification number: H01L27/01 ,  H01L21/0214 ,  H01L21/02247 ,  H01L21/02252 ,  H01L23/3157 ,  H01L24/05 ,  H01L24/06 ,  H01L2224/05567 ,  H01L2224/06102

Abstract: A microelectronic device including an isolation device with a stabilized dielectric. The isolation device includes a lower isolation element, an upper isolation element, and an inorganic dielectric plateau between the lower isolation element and the upper isolation element. The dielectric sidewall of the inorganic dielectric plateau is stabilized in a nitrogen containing plasma which forms a SiOxNy surface on the dielectric sidewall of the inorganic dielectric plateau. The SiOxNy surface on the dielectric sidewall of the inorganic dielectric plateau reduces ingress of moisture into the dielectric stack of the inorganic dielectric plateau.

公开(公告)号：US20240112852A1

公开(公告)日：2024-04-04

申请号：US17957875

申请日：2022-09-30

Applicant: Texas Instruments Incorporated

Inventor： Jeffrey Alan West ,  Byron Lovell Williams ,  Kashyap Barot ,  Sreeram N. S. ,  Viresh Chinchansure

IPC: H01F27/32 ,  H01F41/12

CPC classification number: H01F27/324 ,  H01F41/122 ,  H01F2027/329

Abstract: A microelectronic device includes a galvanic isolation component. The galvanic isolation component includes a lower winding and an upper isolation element over the lower winding. The galvanic isolation component further includes a field suppression structure located interior to the lower winding. The field suppression structure includes a conductive field deflector that is separated from the lower winding by a lateral distance that is half a thickness of the lower winding to twice the thickness of the lower winding. A top surface of the conductive field deflector is substantially coplanar with a bottom surface of the lower winding. The conductive field deflector is electrically connected to a semiconductor material in a substrate. The lower winding is separated from a substrate by a first dielectric layer. The upper isolation element is separated from the lower winding by a second dielectric layer.

公开(公告)号：US11869933B2

公开(公告)日：2024-01-09

申请号：US17398292

申请日：2021-08-10

Applicant: TEXAS INSTRUMENTS INCORPORATED

Inventor： Raja Selvaraj ,  Anant Shankar Kamath ,  Byron Lovell Williams ,  Thomas D. Bonifield ,  John Kenneth Arch

IPC: H01L29/06 ,  H01L27/06 ,  H01L21/761 ,  H01L23/522 ,  H01L23/528 ,  H01L23/00 ,  H01L49/02 ,  H01L21/265

CPC classification number: H01L29/0646 ,  H01L21/265 ,  H01L21/761 ,  H01L23/5223 ,  H01L23/5227 ,  H01L23/5286 ,  H01L24/05 ,  H01L27/0676 ,  H01L28/10 ,  H01L28/20 ,  H01L28/40 ,  H01L28/60 ,  H01L2224/48463

Abstract: Isolator structures for an integrated circuit with reduced effective parasitic capacitance. Disclosed embodiments include an isolator structure with parallel conductive elements forming a capacitor or inductive transformer, overlying a semiconductor structure including a well region of a first conductivity type formed within an tank region of a second conductivity type. The tank region is surrounded by doped regions and a buried doped layer of the first conductivity type, forming a plurality of diodes in series to the substrate. The junction capacitances of the series diodes have the effect of reducing the parasitic capacitance apparent at the isolator.

公开(公告)号：US11848297B2

公开(公告)日：2023-12-19

申请号：US17364807

申请日：2021-06-30

Applicant: Texas Instruments Incorporated

Inventor： Bo-Hsun Pan ,  Chien-Chang Li ,  Hung-Yu Chou ,  Shawn Martin O'Connor ,  Byron Lovell Williams ,  Jeffrey Alan West ,  Zi-Xian Zhan ,  Sheng-Wen Huang

IPC: H01L23/00 ,  H01L23/495 ,  H01L25/065

CPC classification number: H01L24/48 ,  H01L23/4952 ,  H01L23/49575 ,  H01L24/45 ,  H01L24/85 ,  H01L25/0655 ,  H01L2224/45124 ,  H01L2224/45139 ,  H01L2224/45147 ,  H01L2224/45644 ,  H01L2224/45664 ,  H01L2224/48138 ,  H01L2224/48245 ,  H01L2224/48453 ,  H01L2224/48463 ,  H01L2224/48481 ,  H01L2224/85035 ,  H01L2224/85051 ,  H01L2924/182

Abstract: In a described example, an apparatus includes: a package substrate having a die mount portion and lead portions spaced from the die mount portion; a semiconductor die over the die mount portion having bond pads on an active surface facing away from the package substrate; non-gold bond wires forming electrical connections between at least one of the bond pads and one of the lead portions of the package substrate; a bond stitch on bump connection formed between one of the non-gold bond wires and a bond pad of the semiconductor die, comprising a stitch bond formed on a flex stud bump; and dielectric material covering a portion of the package substrate, the semiconductor die, the non-gold bond wires, the stitch bond and the flex stud bump, forming a packaged semiconductor device.

公开(公告)号：US20230056046A1

公开(公告)日：2023-02-23

申请号：US17682762

申请日：2022-02-28

Applicant: Texas Instruments Incorporated

Inventor： Byron Lovell Williams ,  Elizabeth Costner Stewart ,  Jeffrey Alan West ,  Thomas Dyer Bonifield

IPC: H01L23/522 ,  H01L23/528 ,  H01L21/768

Abstract: An electronic device has a conductive shield between first and second regions in a multilevel metallization structure, as well as a capacitor with first and second terminals in the first region, the first terminal laterally overlaps the second terminal by an overlap distance of 1.0 μm to 6.0 μm, the conductive shield includes a first metal line that encircles the first terminal, and the first metal line is spaced apart from the first terminal by a gap distance of 0.5 μm to 1.0 μm.

公开(公告)号：US11024576B1

公开(公告)日：2021-06-01

申请号：US16732296

申请日：2019-12-31

Applicant: TEXAS INSTRUMENTS INCORPORATED

Inventor： Jeffrey Alan West ,  Byron Lovell Williams ,  Thomas Dyer Bonifield

IPC: H01L23/522 ,  H01L23/498 ,  H01L43/04 ,  H01L21/48 ,  H01L21/56

Abstract: A semiconductor package includes a leadframe including a sensor coil between sensor coil leads and further including a plurality of die leads physically and electrically separated from the sensor coil, and a semiconductor die over the leadframe with die contacts electrically connected to the die leads. The semiconductor die includes a sensor operable to detect magnetic fields created by electrical current through the sensor coil, the semiconductor die operable to output a signal representative of the detected magnetic fields via the die leads. The semiconductor package further includes a dielectric underfill filling a gap between the sensor coil and the semiconductor die, and a dielectric mold compound covering the sensor coil and the dielectric underfill and at least partially covering the semiconductor die and the die leads.

公开(公告)号：US10811492B2

公开(公告)日：2020-10-20

申请号：US16176278

申请日：2018-10-31

Applicant: TEXAS INSTRUMENTS INCORPORATED

Inventor： Jeffrey Alan West ,  Byron Lovell Williams ,  John Britton Robbins

IPC: H01L21/027 ,  H01L49/02 ,  H01L23/544 ,  G03F7/20 ,  G03F1/42 ,  G03F7/16

Abstract: A method of fabricating an integrated circuit includes applying photoresist to a MESA dielectric layer of a semiconductor structure, to generate a photoresist layer. The method also includes exposing the photoresist layer with a grayscale mask, to generate an exposed photoresist layer. The photoresist exposed layer includes a thick photoresist pattern in a first region, a thin photoresist pattern in a second region where a height of the thin photoresist pattern is less than half a height of the thick photoresist pattern, and a gap region between the thick photoresist pattern and the thin photoresist pattern.