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    Precision capacitor
    31.
    发明授权
    Precision capacitor 有权

    公开(公告)号：US11569342B2

    公开(公告)日：2023-01-31

    申请号：US16820549

    申请日：2020-03-16

    Applicant: TEXAS INSTRUMENTS INCORPORATED

    Inventor： Poornika Fernandes ,  Luigi Colombo ,  Haowen Bu

    IPC: H01L49/02 ,  C23C16/455 ,  H01L21/677 ,  H01G4/018 ,  H03M1/12

    Abstract: In a described example, a method for forming a capacitor includes: forming a capacitor first plate over a non-conductive substrate; flowing ammonia and nitrogen gas into a plasma enhanced chemical vapor deposition (PECVD) chamber containing the non-conductive substrate; stabilizing a pressure and a temperature in the PECVD chamber; turning on radio frequency high frequency (RF-HF) power to the PECVD chamber; pretreating the capacitor first plate for at least 60 seconds; depositing a capacitor dielectric on the capacitor first plate; and depositing a capacitor second plate on the capacitor dielectric.

    Integrated circuit nanoparticle thermal routing structure over interconnect region
    33.
    发明授权
    Integrated circuit nanoparticle thermal routing structure over interconnect region 有权

    公开(公告)号：US10529641B2

    公开(公告)日：2020-01-07

    申请号：US15361390

    申请日：2016-11-26

    Applicant: Texas Instruments Incorporated

    Inventor： Archana Venugopal ,  Benjamin Stassen Cook ,  Luigi Colombo ,  Robert Reid Doering

    IPC: H01L23/367 ,  H01L21/768 ,  H01L23/373 ,  H01L23/522

    Abstract: An integrated circuit has a thermal routing structure above a top interconnect level. The top interconnect level includes interconnects connected to lower interconnect levels, and does not include bond pads, probe pads, input/output pads, or a redistribution layer to bump bond pads. The thermal routing structure extends over a portion, but not all, of a plane of the integrated circuit containing the top interconnect level. The thermal routing structure includes a layer of nanoparticles in which adjacent nanoparticles are attached to each other. The layer of nanoparticles is free of an organic binder material. The thermal routing structure has a thermal conductivity higher than the metal in the top interconnect level. The layer of nanoparticles is formed by an additive process.

    INTEGRATION OF GRAPHENE AND BORON NITRIDE HETERO-STRUCTURE DEVICE
    35.
    发明申请
    INTEGRATION OF GRAPHENE AND BORON NITRIDE HETERO-STRUCTURE DEVICE 审中-公开

    公开(公告)号：US20190273166A1

    公开(公告)日：2019-09-05

    申请号：US15910817

    申请日：2018-03-02

    Applicant: Texas Instruments Incorporated

    Inventor： Archana Venugopal ,  Luigi Colombo

    IPC: H01L29/786 ,  H01L29/16 ,  H01L29/20 ,  H01L29/267 ,  H01L29/49 ,  H01L29/45 ,  H01L29/66 ,  H01L21/02

    Abstract: A microelectronic device includes a gated graphene component. The gated graphene component has a graphitic layer containing one or more layers of graphene. The graphitic layer has a channel region, a first contact region adjacent to the channel region and a second contact region adjacent to the channel region. A patterned hexagonal boron nitride (hBN) layer is disposed on the graphitic layer above the channel region. A gate is located over the patterned hBN layer above the channel region. A first connection is disposed on the graphitic layer in the first contact region, and a second connection is disposed on the graphitic layer in the second contact region. The patterned hBN layer does not extend completely under the first connection or under the second connection. A method of forming the gated graphene component in the microelectronic device is disclosed.

    LOW CONTACT RESISTANCE GRAPHENE DEVICE INTEGRATION
    38.
    发明申请
    LOW CONTACT RESISTANCE GRAPHENE DEVICE INTEGRATION 审中-公开

    公开(公告)号：US20180308696A1

    公开(公告)日：2018-10-25

    申请号：US15496814

    申请日：2017-04-25

    Applicant: Texas Instruments Incorporated

    Inventor： Luigi Colombo ,  Archana Venugopal

    IPC: H01L21/04 ,  H01L29/16 ,  H01L29/786 ,  H01L29/45

    CPC classification number: H01L21/043 ,  H01L29/1606 ,  H01L29/45 ,  H01L29/78618 ,  H01L29/78684

    Abstract: An electronic device has a graphene layer having one or more atomic layers of graphene, with low resistance contacts that includes a carbon-doped metal layer directly on the graphene layer. The electronic device is formed by forming a carbon-doped metal layer on a substrate layer of the electronic device. The carbon-doped metal layer is subsequently heated to a temperature above which carbon in the carbon-doped metal layer becomes mobile, and subsequently cooled. The carbon in the carbon-doped metal forms the graphene layer under the carbon-doped metal layer and over the substrate layer. The carbon-doped metal layer is removed from an area outside of a contact area, leaving the carbon-doped metal in the contact area to provide a contact layer to the graphene layer.

    Low noise graphene hall sensors, systems and methods of making and using same
    39.
    发明授权
    Low noise graphene hall sensors, systems and methods of making and using same 有权

    公开(公告)号：US10069065B2

    公开(公告)日：2018-09-04

    申请号：US14676233

    申请日：2015-04-01

    Applicant: Texas Instruments Incorporated

    Inventor： Arup Polley ,  Archana Venugopal ,  Robert Reid Doering ,  Luigi Colombo

    IPC: H01L43/10 ,  G01R33/07 ,  H01L43/06

    Abstract: Graphene Hall sensors, magnetic sensor systems and methods for sensing a magnetic field using an adjustable gate voltage to adapt the Hall sensor magnetic field sensitivity according to a control input for environmental or process compensation and/or real-time adaptation for balancing power consumption and minimum detectable field performance. The graphene Hall sensor gate voltage can be modulated and the sensor output signal can be demodulated to combat flicker or other low frequency noise. Also, graphene Hall sensors can be provided with capacitive coupled contacts for reliable low impedance AC coupling to instrumentation amplifiers or other circuits using integral capacitance.

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