公开(公告)号：US20240421045A1

公开(公告)日：2024-12-19

申请号：US18816698

申请日：2024-08-27

Applicant: Texas Instruments Incorporated

Inventor： Christopher Daniel Manack ,  Nazila Dadvand ,  Salvatore Pavone

IPC: H01L23/495 ,  H01L23/00 ,  H01L23/49 ,  H01L23/492 ,  H01L23/532

Abstract: A microelectronic device is formed by thinning a substrate of the microelectronic device from a die attach surface of the substrate, and forming a copper-containing layer on the die attach surface of the substrate. A protective metal layer is formed on the copper-containing layer. Subsequently, the copper-containing layer is attached to a package member having a package die mount area. The protective metal layer may optionally be removed prior to attaching the copper-containing layer to the package member. Alternatively, the protective metal layer may be left on the copper-containing layer when the copper-containing layer is attached to the package member. A structure formed by the method is also disclosed.

公开(公告)号：US12154845B2

公开(公告)日：2024-11-26

申请号：US18389651

申请日：2023-12-19

Applicant: TEXAS INSTRUMENTS INCORPORATED

Inventor： Nazila Dadvand ,  Bernardo Gallegos

IPC: H01L23/495 ,  H01L21/48 ,  H01L21/56 ,  H01L23/00 ,  H01L23/31

Abstract: A semiconductor package includes a pad and leads, the pad and leads including a base metal predominantly including copper, a first plated metal layer predominantly including nickel in contact with the base metal, and a second plated metal layer predominantly including silver in contact with the first plated metal layer. The first plated metal layer has a first plated metal layer thickness of 0.1 to 5 microns, and the second plated metal layer has a second plated metal layer thickness of 0.2 to 5 microns. The semiconductor package further includes an adhesion promotion coating predominantly including silver oxide in contact with the second plated metal layer opposite the first plated metal layer, a semiconductor die mounted on the pad, a wire bond extending between the semiconductor die and a lead of the leads, and a mold compound covering the semiconductor die and the wire bond.

公开(公告)号：US12068221B2

公开(公告)日：2024-08-20

申请号：US16985103

申请日：2020-08-04

Applicant: Texas Instruments Incorporated

Inventor： Nazila Dadvand ,  Christopher Daniel Manack ,  Salvatore Frank Pavone

IPC: H01L23/373 ,  C23C14/16 ,  C23C18/38 ,  C25D3/38 ,  C25D3/46 ,  H01L21/285 ,  H01L21/288 ,  H01L21/768 ,  H01L21/78

CPC classification number: H01L23/3736 ,  C23C14/165 ,  C23C18/38 ,  C25D3/38 ,  C25D3/46 ,  H01L21/2855 ,  H01L21/288 ,  H01L21/76873 ,  H01L21/78

Abstract: Described examples include a process that includes forming a diffusion barrier layer on a backside of a semiconductor wafer. The process also includes forming a seed copper layer on the diffusion barrier layer. The process also includes forming a copper layer on the seed copper layer. The process also includes immersion plating a silver layer on the copper layer.

公开(公告)号：US11694947B2

公开(公告)日：2023-07-04

申请号：US17404946

申请日：2021-08-17

Applicant: Texas Instruments Incorporated

Inventor： Sreenivasan K. Koduri ,  Nazila Dadvand

IPC: H01L23/00 ,  H01L21/48 ,  H01L23/495 ,  H01L21/56 ,  C25D7/00 ,  H01L23/31

CPC classification number: H01L23/49562 ,  C25D7/00 ,  H01L21/4821 ,  H01L21/56 ,  H01L23/3107 ,  H01L23/49582 ,  H01L24/14 ,  H01L2224/14177

Abstract: In some examples, a system comprises a die having multiple electrical connectors extending from a surface of the die and a lead coupled to the multiple electrical connectors. The lead comprises a first conductive member; a first non-solder metal plating stacked on the first conductive member; an electroplated layer stacked on the first non-solder metal plating; a second non-solder metal plating stacked on the electroplated layer; and a second conductive member stacked on the second non-solder metal plating, the second conductive member being thinner than the first conductive member. The system also comprises a molding to at least partially encapsulate the die and the lead.

公开(公告)号：US11587858B2

公开(公告)日：2023-02-21

申请号：US17323939

申请日：2021-05-18

Applicant: Texas Instruments Incorporated

Inventor： Nazila Dadvand ,  Christopher Daniel Manack ,  Salvatore Frank Pavone

IPC: H01L23/498 ,  H01L23/00 ,  H01L23/495 ,  B23K1/00 ,  C25D5/12 ,  C25D5/18 ,  C25D7/12 ,  C25D3/22 ,  B23K101/36 ,  C25D3/12

Abstract: A microelectronic device has bump bond structures on input/output (I/O) pads. The bump bond structures include copper-containing pillars, a barrier layer including cobalt and zinc on the copper-containing pillars, and tin-containing solder on the barrier layer. The barrier layer includes 0.1 weight percent to 50 weight percent cobalt and an amount of zinc equivalent to a layer of pure zinc 0.05 microns to 0.5 microns thick. A lead frame has a copper-containing member with a similar barrier layer in an area for a solder joint. Methods of forming the microelectronic device are disclosed.

公开(公告)号：US20220208640A1

公开(公告)日：2022-06-30

申请号：US17138541

申请日：2020-12-30

Applicant: Texas Instruments Incorporated

Inventor： Benjamin Stassen Cook ,  Nazila Dadvand ,  Archana Venugopal ,  Daniel Lee Revier

IPC: H01L23/373 ,  H01L23/532 ,  H01L21/78 ,  H01L21/3205 ,  H01L21/683

Abstract: In described examples, a semiconductor wafer with a thermally conductive surface layer comprises a bulk semiconductor layer having a first surface and a second surface, circuitry on the first surface, a metallic layer attached to the first surface or the second surface, and a graphene layer attached to the metallic layer. The first surface opposes the second surface. The metallic layer comprises a transition metal.

公开(公告)号：US11254775B2

公开(公告)日：2022-02-22

申请号：US16229971

申请日：2018-12-21

Applicant: TEXAS INSTRUMENTS INCORPORATED

Inventor： Nazila Dadvand ,  Benjamin Stassen Cook ,  Archana Venugopal ,  Luigi Colombo

IPC: C08F292/00 ,  C08F8/42 ,  C08L33/12 ,  C08K3/08 ,  C08K7/00 ,  C08J5/24 ,  G03F1/78 ,  C08K3/04 ,  C08J5/00 ,  C08L25/06

Abstract: A composite material comprises a polymer matrix having microstructure filler materials that comprise a plurality of interconnected units wherein the units are formed of connected tubes. The tubes may be formed by photo-initiating the polymerization of a monomer in a pattern of interconnected units to form a polymer microlattice, removing unpolymerized monomer, coating the polymer microlattice with a metal, removing the polymer microlattice to leave a metal microlattice, growing or depositing a material on the metal microlattice such as graphene, hexagonal boron nitride or other ceramic, and subsequently removing the metal microlattice.

公开(公告)号：US20220005760A1

公开(公告)日：2022-01-06

申请号：US17475295

申请日：2021-09-14

Applicant: TEXAS INSTRUMENTS INCORPORATED

Inventor： Nazila Dadvand ,  Christopher Daniel Manack

IPC: H01L23/522 ,  H01L23/31 ,  H01L23/528 ,  H01L23/532 ,  H01L21/768

Abstract: A die includes a semiconductor layer, an electrical contact on a first side of the semiconductor layer, a backside electrical contact layer on second side of the semiconductor layer. The die further includes a zinc layer over at least one of the electrical contact or the backside electrical contact layer of the die, and a conversion coating over the zinc layer. The conversion coating includes at least one of zirconium and vanadium. As part of an embedded die package including the die, at least a portion of the conversion coating may adjacent to an electrically insulating substrate of the embedded die package.

公开(公告)号：US10957635B2

公开(公告)日：2021-03-23

申请号：US16359628

申请日：2019-03-20

Applicant: Texas Instruments Incorporated

Inventor： Nazila Dadvand ,  Sreenivasan Koduri ,  Benjamin Stassen Cook

IPC: H01L21/48 ,  H01L21/56 ,  H01L25/18 ,  H01L25/065 ,  C25D7/12 ,  C25D3/38 ,  H01L23/00 ,  H01L23/13 ,  H01L23/14 ,  H01L23/31 ,  H01L23/367 ,  H01L23/495 ,  H01L23/498 ,  H01L23/544

Abstract: A packaged semiconductor device includes a metal substrate having a first and second through-hole aperture having an outer ring, and metal pads around the apertures on dielectric pads. A first and second semiconductor die have a back side metal (BSM) layer on its bottom side are mounted top side up on a top portion of the apertures. A metal die attach layer is directly between the BSM layer and walls of the metal substrate bounding the apertures to provide a die attachment for the first and the second semiconductor die that fills a bottom portion of the apertures. Leads contact the metal pads, wherein the leads include a distal portion that extends beyond the metal substrate. Bondwires are between the metal pads and bond pads on the first and second semiconductor die, and a mold compound provides encapsulation for the packaged semiconductor device.

公开(公告)号：US20210013167A1

公开(公告)日：2021-01-14

申请号：US16506494

申请日：2019-07-09

Applicant: Texas Instruments Incorporated

Inventor： Nazila Dadvand

IPC: H01L23/00 ,  H01L21/78

Abstract: A microelectronic device has a solder-free package lead extending through an electrically non-conductive package structure to an exterior of the microelectronic device. The package lead includes a pillar contacting a terminal on a die and extending partway through the package structure, and an external lead electrically coupled to the pillar and extending to an exterior of the microelectronic device. The package lead is free of a solder joint. The microelectronic device may be formed by forming an access cavity package structure, to expose the pillar, and forming the external lead by a plating process. The microelectronic device may be formed by providing an external lead lamina containing the external lead, and forming a plated metal joint by a plating process that connects the external lead to the pillar.