公开(公告)号：US11955515B2

公开(公告)日：2024-04-09

申请号：US17815761

申请日：2022-07-28

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Shih-Chuan Chiu ,  Chia-Hao Chang ,  Cheng-Chi Chuang ,  Chih-Hao Wang ,  Huan-Chieh Su ,  Chun-Yuan Chen ,  Li-Zhen Yu ,  Yu-Ming Lin

IPC: H01L29/06 ,  H01L21/8234 ,  H01L29/423

CPC classification number: H01L29/0673 ,  H01L21/823418 ,  H01L29/42392

Abstract: A semiconductor device with dual side source/drain (S/D) contact structures and a method of fabricating the same are disclosed. The method includes forming a fin structure on a substrate, forming a superlattice structure on the fin structure, forming first and second S/D regions within the superlattice structure, forming a gate structure between the first and second S/D regions, forming first and second contact structures on first surfaces of the first and second S/D regions, and forming a third contact structure, on a second surface of the first S/D region, with a work function metal (WFM) silicide layer and a dual metal liner. The second surface is opposite to the first surface of the first S/D region and the WFM silicide layer has a work function value closer to a conduction band energy than a valence band energy of a material of the first S/D region.

公开(公告)号：US11916133B2

公开(公告)日：2024-02-27

申请号：US17676699

申请日：2022-02-21

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Li-Zhen Yu ,  Lin-Yu Huang ,  Chia-Hao Chang ,  Cheng-Chi Chuang ,  Yu-Ming Lin ,  Chih-Hao Wang

IPC: H01L29/66 ,  H01L21/768

CPC classification number: H01L29/6656 ,  H01L21/76832 ,  H01L21/76834 ,  H01L29/66545

Abstract: Semiconductor devices and methods of forming the same are provided. In one embodiment, a semiconductor device includes a gate structure sandwiched between and in contact with a first spacer feature and a second spacer feature, a top surface of the first spacer feature and a top surface of the second spacer feature extending above a top surface of the gate structure, a gate self-aligned contact (SAC) dielectric feature over the first spacer feature and the second spacer feature, a contact etch stop layer (CESL) over the gate SAC dielectric feature, a dielectric layer over the CESL, a gate contact feature extending through the dielectric layer, the CESL, the gate SAC dielectric feature, and between the first spacer feature and the second spacer feature to be in contact with the gate structure, and a liner disposed between the first spacer feature and the gate contact feature.

公开(公告)号：US11916128B2

公开(公告)日：2024-02-27

申请号：US18175137

申请日：2023-02-27

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Min Cao ,  Pei-Yu Wang ,  Sai-Hooi Yeong ,  Ching-Wei Tsai ,  Kuan-Lun Cheng ,  Chih-Hao Wang

IPC: H01L21/00 ,  H01L21/02 ,  H01L21/8238 ,  H01L27/092 ,  H01L29/423 ,  H01L29/51 ,  H01L29/66 ,  H01L29/78

CPC classification number: H01L29/516 ,  H01L21/0206 ,  H01L21/823828 ,  H01L21/823857 ,  H01L27/092 ,  H01L29/42364 ,  H01L29/513 ,  H01L29/517 ,  H01L29/6684 ,  H01L29/78391

Abstract: The present disclosure provides a method of forming a semiconductor device including an nFET structure and a pFET structure where each of the nFET and pFET structures include a semiconductor substrate and a gate trench. The method includes depositing an interfacial layer in each gate trench, depositing a first ferroelectric layer over the interfacial layer, removing the first ferroelectric layer from the nFET structure, depositing a metal oxide layer in each gate trench, depositing a second ferroelectric layer over the metal oxide layer, removing the second ferroelectric layer from the pFET structure, and depositing a gate electrode in each gate trench.

公开(公告)号：US11916125B2

公开(公告)日：2024-02-27

申请号：US17871509

申请日：2022-07-22

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Chih-Chao Chou ,  Kuo-Cheng Chiang ,  Shi Ning Ju ,  Wen-Ting Lan ,  Chih-Hao Wang

IPC: H01L29/423 ,  H01L29/08 ,  H01L29/10 ,  H01L29/66

CPC classification number: H01L29/42392 ,  H01L29/0847 ,  H01L29/1033 ,  H01L29/66545

Abstract: Semiconductor device and the manufacturing method thereof are disclosed. An exemplary semiconductor device comprises a dielectric layer formed over a conductive feature; a semiconductor stack formed over the dielectric layer, wherein the semiconductor stack including semiconductor layers stacked up and separated from each other; a first metal gate structure and a second metal gate structure formed over a channel region of the semiconductor stack, wherein the first metal gate structure and the second metal gate structure wrap each of the semiconductor layers of the semiconductor stack; and a first epitaxial feature disposed between the first metal gate structure and the second metal gate structure over a first source/drain region of the semiconductor stack, wherein the first epitaxial feature extends through the dielectric layer and contacts the conductive feature.

公开(公告)号：US20240021707A1

公开(公告)日：2024-01-18

申请号：US18364574

申请日：2023-08-03

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Li-Zhen Yu ,  Lin-Yu Huang ,  Chia-Hao Chang ,  Cheng-Chi Chuang ,  Yu-Ming Lin ,  Chih-Hao Wang

IPC: H01L29/66 ,  H01L21/768

CPC classification number: H01L29/6656 ,  H01L21/76832 ,  H01L21/76834 ,  H01L29/66545

Abstract: Semiconductor devices and methods of forming the same are provided. In one embodiment, a semiconductor device includes a gate structure sandwiched between and in contact with a first spacer feature and a second spacer feature, a top surface of the first spacer feature and a top surface of the second spacer feature extending above a top surface of the gate structure, a gate self-aligned contact (SAC) dielectric feature over the first spacer feature and the second spacer feature, a contact etch stop layer (CESL) over the gate SAC dielectric feature, a dielectric layer over the CESL, a gate contact feature extending through the dielectric layer, the CESL, the gate SAC dielectric feature, and between the first spacer feature and the second spacer feature to be in contact with the gate structure, and a liner disposed between the first spacer feature and the gate contact feature.

公开(公告)号：US11855096B2

公开(公告)日：2023-12-26

申请号：US17728247

申请日：2022-04-25

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Jui-Chien Huang ,  Shih-Cheng Chen ,  Chih-Hao Wang ,  Kuo-Cheng Chiang ,  Zhi-Chang Lin ,  Jung-Hung Chang ,  Lo-Heng Chang ,  Shi Ning Ju ,  Guan-Lin Chen

IPC: H01L27/092 ,  H01L29/06 ,  H01L29/66 ,  H01L29/78 ,  H01L21/8234

CPC classification number: H01L27/0924 ,  H01L21/823412 ,  H01L21/823431 ,  H01L29/0665 ,  H01L29/6656 ,  H01L29/66818 ,  H01L29/7851

Abstract: According to one example, a semiconductor device includes a substrate and a fin stack that includes a plurality of nanostructures, a gate device surrounding each of the nanostructures, and inner spacers along the gate device and between the nanostructures. A width of the inner spacers differs between different layers of the fin stack.

公开(公告)号：US11855079B2

公开(公告)日：2023-12-26

申请号：US17484956

申请日：2021-09-24

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Kuo-Cheng Chiang ,  Jung-Chien Cheng ,  Shi-Ning Ju ,  Guan-Lin Chen ,  Chih-Hao Wang

IPC: H01L27/088 ,  H01L29/06 ,  H01L29/66 ,  H01L29/423 ,  H01L21/762

CPC classification number: H01L27/088 ,  H01L21/76224 ,  H01L29/0649 ,  H01L29/0673 ,  H01L29/4232 ,  H01L29/66477

Abstract: An integrated circuit includes a first nanosheet transistor and a second nanosheet transistor on a substrate. The first and second nanosheet each include gate electrodes. A gate isolation structure extends from a backside of the substrate between the gate electrodes. The gate isolation structure physically and electrically isolates the first and second gate electrodes from each other.

公开(公告)号：US11854902B2

公开(公告)日：2023-12-26

申请号：US17869132

申请日：2022-07-20

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Kuo-Cheng Chiang ,  Shi Ning Ju ,  Kuan-Lun Cheng ,  Chih-Hao Wang

IPC: H01L21/8234 ,  H01L29/78 ,  H01L29/66 ,  H01L21/768 ,  H01L27/088

CPC classification number: H01L21/823475 ,  H01L21/76832 ,  H01L21/76876 ,  H01L21/823431 ,  H01L21/823437 ,  H01L21/823468 ,  H01L27/0886 ,  H01L29/66545 ,  H01L29/66795 ,  H01L29/785 ,  H01L2029/7858

Abstract: Examples of an integrated circuit with an interconnect structure that includes a buried interconnect conductor and a method for forming the integrated circuit are provided herein. In some examples, the method includes receiving a substrate that includes a plurality of fins extending from a remainder of the substrate. A spacer layer is formed between the plurality of fins, and a buried interconnect conductor is formed on the spacer layer between the plurality of fins. A set of capping layers is formed on the buried interconnect conductor between the plurality of fins. A contact recess is etched through the set of capping layers that exposes the buried interconnect conductor, and a contact is formed in the contact recess that is electrically coupled to the buried interconnect conductor.

公开(公告)号：US20230411499A1

公开(公告)日：2023-12-21

申请号：US18361556

申请日：2023-07-28

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Kuan-Ting Pan ,  Huan-Chieh Su ,  Jia-Chuan You ,  Shi Ning Ju ,  Kuo-Cheng Chiang ,  Yi-Ruei Jhan ,  Li-Yang Chuang ,  Chih-Hao Wang

IPC: H01L29/66 ,  H01L21/8234 ,  H01L29/06

CPC classification number: H01L29/6681 ,  H01L29/0669 ,  H01L29/0649 ,  H01L21/823431

Abstract: A semiconductor structure includes a plurality of fin structures extending along a first direction, a plurality of gate structure segments positioned along a line extending in a second direction, the second direction being orthogonal to the first direction, wherein the gate structure segments are separated by dummy fin structures. The semiconductor structure further includes a conductive layer disposed over both the gate structure segments and the dummy fin structures to electrically connect at least some of the gate structure segments, and a cut feature aligned with one of the dummy fin structures and positioned to electrically isolate gate structure segments on both sides of the one of the dummy fin structures.

公开(公告)号：US20230411494A1

公开(公告)日：2023-12-21

申请号：US18366908

申请日：2023-08-08

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Sai-Hooi Yeong ,  Chi-On Chui ,  Kai-Hsuan Lee ,  Kuan-Lun Cheng ,  Chih-Hao Wang

IPC: H01L29/66 ,  H01L21/8234 ,  H01L29/78

CPC classification number: H01L29/66545 ,  H01L29/66795 ,  H01L21/823431 ,  H01L29/785 ,  H01L21/823468

Abstract: A method includes forming a fin over a substrate, forming an isolation structure on the substrate, and forming first and second mandrel patterns over the fin. The fin extends upwardly through the isolation structure. The fin extends lengthwise along a first direction, and each of the first and second mandrel patterns extends lengthwise along a second direction perpendicular to the first direction. The method also includes depositing a sacrificial feature between the first and second mandrel patterns, removing the first and second mandrel patterns, forming a spacer layer in physical contact with sidewalls of the sacrificial feature, removing the sacrificial feature to form a trench, and forming a metal gate stack in the trench. The sacrificial feature extends lengthwise along the second direction.