公开(公告)号：US11942375B2

公开(公告)日：2024-03-26

申请号：US17404443

申请日：2021-08-17

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Hsing-Hui Hsu ,  Po-Nien Chen ,  Yi-Hsuan Chung ,  Bo-Shiuan Shie ,  Chih-Yung Lin

IPC: H01L21/8238 ,  H01L21/02 ,  H01L27/092 ,  H01L29/66 ,  H01L29/78

CPC classification number: H01L21/823821 ,  H01L21/02532 ,  H01L21/823807 ,  H01L21/823814 ,  H01L21/823842 ,  H01L21/823871 ,  H01L27/0924 ,  H01L27/0928 ,  H01L29/66545 ,  H01L29/66795 ,  H01L29/785 ,  H01L21/823892 ,  H01L29/7848

Abstract: A structure and a formation method of a semiconductor device are provided. The method includes forming a first semiconductor fin and a second semiconductor fin over a semiconductor substrate. The second semiconductor fin is wider than the first semiconductor fin. The method also includes forming a gate stack over the semiconductor substrate, and the gate stack extends across the first semiconductor fin and the second semiconductor fin. The method further includes forming a first source/drain structure on the first semiconductor fin, and the first source/drain structure is p-type doped. In addition, the method includes forming a second source/drain structure on the second semiconductor fin, and the second source/drain structure is n-type doped.

公开(公告)号：US20230207320A1

公开(公告)日：2023-06-29

申请号：US18171530

申请日：2023-02-20

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Hsiao-Han Liu ,  Hoppy Lee ,  Chung-Yu Chiang ,  Po-Nien Chen ,  Chih-Yung Lin

IPC: H01L21/033 ,  H01L27/07 ,  H01L21/8234 ,  H01L29/66 ,  H01L21/768

CPC classification number: H01L21/0337 ,  H01L21/76829 ,  H01L21/823431 ,  H01L21/823468 ,  H01L21/823481 ,  H01L27/0733 ,  H01L28/60 ,  H01L29/66545

Abstract: Examples of an integrated circuit with a capacitor structure and a method for forming the integrated circuit are provided herein. In some examples, an integrated circuit device includes a substrate and a trench isolation material disposed on the substrate. An isolation structure is disposed on the trench isolation material. A first electrode disposed on the isolation structure, and a second electrode disposed on the isolation structure. A capacitor dielectric is disposed on the isolation structure between the first electrode and the second electrode. In some such examples, the isolation structure includes a first hard mask disposed on the trench isolation material, a dielectric disposed on the first hard mask, and a second hard mask disposed on the dielectric.

公开(公告)号：US11587790B2

公开(公告)日：2023-02-21

申请号：US17114108

申请日：2020-12-07

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Hsiao-Han Liu ,  Hoppy Lee ,  Chung-Yu Chiang ,  Po-Nien Chen ,  Chih-Yung Lin

IPC: H01L21/033 ,  H01L49/02 ,  H01L27/07 ,  H01L21/8234 ,  H01L29/66 ,  H01L21/768

Abstract: Examples of an integrated circuit with a capacitor structure and a method for forming the integrated circuit are provided herein. In some examples, an integrated circuit device includes a substrate and a trench isolation material disposed on the substrate. An isolation structure is disposed on the trench isolation material. A first electrode disposed on the isolation structure, and a second electrode disposed on the isolation structure. A capacitor dielectric is disposed on the isolation structure between the first electrode and the second electrode. In some such examples, the isolation structure includes a first hard mask disposed on the trench isolation material, a dielectric disposed on the first hard mask, and a second hard mask disposed on the dielectric.

公开(公告)号：US11387321B2

公开(公告)日：2022-07-12

申请号：US16881467

申请日：2020-05-22

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Jiefeng Lin ,  Jeng-Ya Yeh ,  Chih-Yung Lin

IPC: H01L21/02 ,  H01L29/02 ,  H01L29/08 ,  H01L29/417 ,  H01L21/324 ,  H01L21/762 ,  H01L21/306

Abstract: The present disclosure provides a method that includes receiving a semiconductor substrate that includes an integrated circuit (IC) cell and a well tap cell surrounding the IC cell; forming first fin active regions in the well tap cell and second fin active regions in the IC cell; forming a hard mask within the well tap cell, wherein the hard mask includes openings that define first source/drain (S/D) regions on the first fin active region of the well tap cell; forming gate stacks on the second fin active regions within the IC cell and absent from the well tap cell, wherein the gate stacks define second S/D regions on the second fin active regions; epitaxially growing first S/D features in the first S/D regions using the hard mask to constrain the epitaxially growing; and forming contacts landing on the first S/D features within the well tap cell.

公开(公告)号：US11210447B2

公开(公告)日：2021-12-28

申请号：US16414488

申请日：2019-05-16

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Jiefeng Jeff Lin ,  Chih-Yung Lin ,  Dian-Sheg Yu ,  Hsiao-Lan Yang ,  Jhon Jhy Liaw

IPC: H01L27/088 ,  G06F30/398 ,  H01L29/78 ,  H01L21/8234 ,  H01L23/522

Abstract: The first type of semiconductor device includes a first fin structure extending in a first direction, a first gate, and a first slot contact disposed over the first fin structure. The first gate extends in a second direction and has a first gate dimension measured in the first direction. The first slot contact has a first slot contact dimension measured in the first direction. A second type of semiconductor device includes: a second fin structure extending in a third direction, a second gate, and a second slot contact disposed over the second fin structure. The second gate extends in a fourth direction and has a second gate dimension measured in the third direction. The second slot contact has a second slot contact dimension measured in the third direction. The second slot contact dimension is greater than the second gate dimension and greater than the first slot contact dimension.

公开(公告)号：US20210327765A1

公开(公告)日：2021-10-21

申请号：US17363837

申请日：2021-06-30

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Pei-Hsun Wu ,  Ming-Hung Han ,  Po-Nien Chen ,  Chih-Yung Lin

IPC: H01L21/8234 ,  H01L29/66 ,  H01L27/088 ,  H01L29/78 ,  H01L29/06 ,  H01L29/10 ,  H01L29/423

Abstract: A semiconductor device includes a substrate having a first region and a second region, a first transistor in the first region, a second transistor in the first region, and a third transistor in the second region. The first transistor includes a first channel layer and a first gate dielectric layer on the first channel layer. The second transistor includes a second channel layer and a second gate dielectric layer on the second channel layer. The second gate dielectric layer is thicker than the first gate dielectric layer. The third transistor includes a third channel layer and a third gate dielectric layer on the third channel layer. The third gate dielectric layer is thicker than the second gate dielectric layer.

公开(公告)号：US20210272852A1

公开(公告)日：2021-09-02

申请号：US17246998

申请日：2021-05-03

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Ta-Chun Lin ,  Buo-Chin Hsu ,  Kuo-Hua Pan ,  Jhon Jhy Liaw ,  Chih-Yung Lin

IPC: H01L21/8234 ,  H01L27/088 ,  H01L29/06 ,  H01L21/311 ,  H01L29/66 ,  H01L21/3105

Abstract: A structure includes a fin on a substrate; first and second gate stacks over the fin and including first and second gate dielectric layers and first and second gate electrodes respectively; and a dielectric gate over the fin and between the first and second gate stacks. The dielectric gate includes a dielectric material layer on a third gate dielectric layer. In a cross-sectional view cut along a direction parallel to a lengthwise direction of the fin and offset from the fin, the first gate dielectric layer forms a first U shape, the third gate dielectric layer forms a second U shape, a portion of the first gate electrode is disposed within the first U shape, a portion of the dielectric material layer is disposed within the second U shape, and a portion of an interlayer dielectric layer is disposed laterally between the first and the second U shapes.

公开(公告)号：US11094597B2

公开(公告)日：2021-08-17

申请号：US16526692

申请日：2019-07-30

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Hsing-Hui Hsu ,  Po-Nien Chen ,  Yi-Hsuan Chung ,  Bo-Shiuan Shie ,  Chih-Yung Lin

IPC: H01L29/49 ,  H01L21/84 ,  H01L21/324 ,  H01L29/78 ,  H01L29/51 ,  H01L21/8238 ,  H01L29/66 ,  H01L21/02 ,  H01L27/092

Abstract: A structure and a formation method of a semiconductor device are provided. The method includes forming a first semiconductor fin and a second semiconductor fin over a semiconductor substrate. The second semiconductor fin is wider than the first semiconductor fin. The method also includes forming a gate stack over the semiconductor substrate, and the gate stack extends across the first semiconductor fin and the second semiconductor fin. The method further includes forming a first source/drain structure on the first semiconductor fin, and the first source/drain structure is p-type doped. In addition, the method includes forming a second source/drain structure on the second semiconductor fin, and the second source/drain structure is n-type doped.

公开(公告)号：US20210202323A1

公开(公告)日：2021-07-01

申请号：US16728154

申请日：2019-12-27

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Pei-Hsun Wu ,  Ming-Hung Han ,  Po-Nien Chen ,  Chih-Yung Lin

IPC: H01L21/8234 ,  H01L27/088 ,  H01L29/78 ,  H01L29/66

Abstract: A semiconductor device includes a substrate; an I/O device over the substrate; and a core device over the substrate. The I/O device includes a first gate structure having an interfacial layer; a first high-k dielectric stack over the interfacial layer; and a conductive layer over and in physical contact with the first high-k dielectric stack. The core device includes a second gate structure having the interfacial layer; a second high-k dielectric stack over the interfacial layer; and the conductive layer over and in physical contact with the second high-k dielectric stack. The first high-k dielectric stack includes the second high-k dielectric stack and a third dielectric layer.

公开(公告)号：US10861928B2

公开(公告)日：2020-12-08

申请号：US16183113

申请日：2018-11-07

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Hsiao-Han Liu ,  Hoppy Lee ,  Chung-Yu Chiang ,  Po-Nien Chen ,  Chih-Yung Lin

IPC: H01L49/02 ,  H01L27/07 ,  H01L21/8234 ,  H01L29/66 ,  H01L21/768 ,  H01L21/033

Abstract: Examples of an integrated circuit with a capacitor structure and a method for forming the integrated circuit are provided herein. In some examples, an integrated circuit device includes a substrate and a trench isolation material disposed on the substrate. An isolation structure is disposed on the trench isolation material. A first electrode disposed on the isolation structure, and a second electrode disposed on the isolation structure. A capacitor dielectric is disposed on the isolation structure between the first electrode and the second electrode. In some such examples, the isolation structure includes a first hard mask disposed on the trench isolation material, a dielectric disposed on the first hard mask, and a second hard mask disposed on the dielectric.