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    METHOD OF MANUFACTURING A SEMICONDUCTOR DEVICE
    37.
    发明申请
    METHOD OF MANUFACTURING A SEMICONDUCTOR DEVICE 有权

    公开(公告)号：US20210074538A1

    公开(公告)日：2021-03-11

    申请号：US16991996

    申请日：2020-08-12

    Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.

    Inventor： An-Ren ZI ,  Ching-Yu CHANG ,  Chin-Hsiang LIN

    IPC: H01L21/027 ,  H01L21/67

    Abstract: A method of manufacturing a semiconductor device includes forming a first protective layer over an edge portion of a first main surface of a semiconductor substrate. A metal-containing photoresist layer is formed over the first main surface of the semiconductor substrate. The first protective layer is removed, and the metal-containing photoresist layer is selectively exposed to actinic radiation. A second protective layer is formed over the edge portion of the first main surface of the semiconductor substrate. The selectively exposed photoresist layer is developed to form a patterned photoresist layer, and the second protective layer is removed.

    CAPPING LAYER FOR GATE ELECTRODES
    38.
    发明申请
    CAPPING LAYER FOR GATE ELECTRODES 有权

    公开(公告)号：US20210057543A1

    公开(公告)日：2021-02-25

    申请号：US16548918

    申请日：2019-08-23

    Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.

    Inventor： Chin-Hsiang LIN ,  Teng-Chun TSAI ,  Akira MINEJI ,  Huang-Lin CHAO

    IPC: H01L29/66 ,  H01L29/45 ,  H01L29/49 ,  H01L29/78 ,  H01L21/311 ,  H01L21/321

    Abstract: The present disclosure describes a method for forming a hard mask on a transistor's gate structure that minimizes gate spacer loss and gate height loss during the formation of self-aligned contact openings. The method includes forming spacers on sidewalls of spaced apart gate structures and disposing a dielectric layer between the gate structures. The method also includes etching top surfaces of the gate structures and top surfaces of the spacers with respect to a top surface of the dielectric layer. Additionally, the method includes depositing a hard mask layer haying a metal containing dielectric layer over the etched top surfaces of the gate structures and the spacers and etching the dielectric layer with an etching chemistry to form contact openings between the spacers, where the hard mask layer has a lower etch rate than the spacers when exposed to the etching chemistry.

    LAYOUT MODIFICATION METHOD FOR EXPOSURE MANUFACTURING PROCESS
    39.
    发明申请
    LAYOUT MODIFICATION METHOD FOR EXPOSURE MANUFACTURING PROCESS 审中-公开

    公开(公告)号：US20200350306A1

    公开(公告)日：2020-11-05

    申请号：US16933127

    申请日：2020-07-20

    Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

    Inventor： Hung-Wen CHO ,  Fu-Jye LIANG ,  Chun-Kuang CHEN ,  Chih-Tsung SHIH ,  Li-Jui CHEN ,  Po-Chung CHENG ,  Chin-Hsiang LIN

    IPC: H01L27/02 ,  G03F1/36 ,  G06F30/30 ,  G06F30/39

    Abstract: A layout modification method for fabricating a semiconductor device is provided. Uniformity of critical dimensions of a first portion and a second portion in a patterned layer are calculated by using a layout for an exposure manufacturing process to produce the semiconductor device. A width of the second portion equals a penumbra size of the exposure manufacturing process, and the penumbra size is utilized to indicate which area of the patterned layer is affected by light leakage exposure from another exposure manufacturing process. Non-uniformity between the first and second portions of the patterned layer is compensated according to the uniformity of critical dimensions to generate a modified layout. The patterned layer includes a plurality of absorbers, and a first width of the absorbers is the first portion is less than a second width of the absorbers in the second portion the second portion.

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