公开(公告)号：US20210132310A1

公开(公告)日：2021-05-06

申请号：US17121060

申请日：2020-12-14

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Chen-Hua Yu ,  Hsing-Kuo Hsia ,  Sung-Hui Huang ,  Kuan-Yu Huang ,  Kuo-Chiang Ting ,  Shang-Yun Hou ,  Chi-Hsi Wu

IPC: G02B6/42 ,  H01L23/00

Abstract: A structure including a photonic integrated circuit die, an electric integrated circuit die, a semiconductor dam, and an insulating encapsulant is provided. The photonic integrated circuit die includes an optical input/output portion and a groove located in proximity of the optical input/output portion, wherein the groove is adapted for lateral insertion of at least one optical fiber. The electric integrated circuit die is disposed over and electrically connected to the photonic integrated circuit die. The semiconductor dam is disposed over the photonic integrated circuit die. The insulating encapsulant is disposed over the photonic integrated circuit die and laterally encapsulates the electric integrated circuit die and the semiconductor dam.

公开(公告)号：US10790254B2

公开(公告)日：2020-09-29

申请号：US16277806

申请日：2019-02-15

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Kuan-Yu Huang ,  Sung-Hui Huang ,  Shu-Chia Hsu ,  Leu-Jen Chen ,  Yi-Wei Liu ,  Shang-Yun Hou ,  Jui-Hsieh Lai ,  Tsung-Yu Chen ,  Chien-Yuan Huang ,  Yu-Wei Chen

IPC: H01L29/40 ,  H01L21/44 ,  H01L23/00 ,  H01L21/56 ,  H01L23/522

Abstract: A chip package structure is provided. The chip package structure includes a substrate having a first surface and a second surface opposite to the first surface. The chip package structure includes a first chip structure and a second chip structure over the first surface. The chip package structure includes a protective layer over the first surface and surrounding the first chip structure and the second chip structure. A portion of the protective layer is between the first chip structure and the second chip structure. The chip package structure includes a first anti-warpage bump over the second surface and extending across the portion of the protective layer. The chip package structure includes a conductive bump over the second surface and electrically connected to the first chip structure or the second chip structure. The first anti-warpage bump is wider than the conductive bump.

公开(公告)号：US12080617B2

公开(公告)日：2024-09-03

申请号：US18194876

申请日：2023-04-03

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Yu-Wei Chen ,  Li-Chung Kuo ,  Ying-Ching Shih ,  Szu-Wei Lu ,  Jing-Cheng Lin ,  Long Hua Lee ,  Kuan-Yu Huang

IPC: H01L23/31 ,  H01L21/56 ,  H01L23/00 ,  H01L23/498 ,  H01L25/065

CPC classification number: H01L23/3135 ,  H01L21/563 ,  H01L23/3128 ,  H01L23/49816 ,  H01L24/16 ,  H01L25/0657 ,  H01L2224/16225 ,  H01L2225/0651 ,  H01L2225/0652

Abstract: A method for forming an underfill structure and semiconductor packages including the underfill structure are disclosed. In an embodiment, the semiconductor package may include a package including an integrated circuit die; an interposer bonded to the integrated circuit die by a plurality of die connectors; and an encapsulant surrounding the integrated circuit die. The semiconductor package may further include a package substrate bonded to the interposer by a plurality of conductive connectors; a first underfill between the package and the package substrate, the first underfill having a first coefficient of thermal expansion (CTE); and a second underfill surrounding the first underfill, the second underfill having a second CTE less than the first CTE.

公开(公告)号：US11916023B2

公开(公告)日：2024-02-27

申请号：US17012255

申请日：2020-09-04

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Sung-Hui Huang ,  Da-Cyuan Yu ,  Kuan-Yu Huang ,  Pai Yuan Li ,  Hsiang-Fan Lee

IPC: H01L21/56 ,  H01L21/48 ,  H01L23/00 ,  H01L23/31 ,  H01L23/367 ,  H01L23/373 ,  H01L23/498 ,  H01L25/00 ,  H01L25/065 ,  H01L25/18

CPC classification number: H01L23/562 ,  H01L21/4853 ,  H01L21/4857 ,  H01L21/486 ,  H01L21/4882 ,  H01L21/563 ,  H01L21/565 ,  H01L23/3114 ,  H01L23/3128 ,  H01L23/3135 ,  H01L23/3675 ,  H01L23/3733 ,  H01L23/3736 ,  H01L23/3737 ,  H01L23/49822 ,  H01L23/49827 ,  H01L23/49838 ,  H01L24/32 ,  H01L24/83 ,  H01L25/0655 ,  H01L25/18 ,  H01L25/50 ,  H01L23/367 ,  H01L24/16 ,  H01L24/73 ,  H01L24/97 ,  H01L2224/13147 ,  H01L2224/13155 ,  H01L2224/16225 ,  H01L2224/16227 ,  H01L2224/26175 ,  H01L2224/32225 ,  H01L2224/73204 ,  H01L2224/73253 ,  H01L2224/83385 ,  H01L2224/83951 ,  H01L2224/92225 ,  H01L2924/00014 ,  H01L2924/10158 ,  H01L2924/15174 ,  H01L2924/15311 ,  H01L2924/16152 ,  H01L2924/165 ,  H01L2924/181 ,  H01L2924/18161 ,  H01L2924/35121 ,  H01L2224/73204 ,  H01L2224/16225 ,  H01L2224/32225 ,  H01L2924/00012 ,  H01L2924/181 ,  H01L2924/00012 ,  H01L2924/15311 ,  H01L2224/73204 ,  H01L2224/16225 ,  H01L2224/32225 ,  H01L2924/00012 ,  H01L2924/00014 ,  H01L2224/13099

Abstract: A package includes a package component, a device die over and bonded to the package component, a metal cap having a top portion over the device die, and a thermal interface material between and contacting the device die and the metal cap. The thermal interface material includes a first portion directly over an inner portion of the device die, and a second portion extending directly over a corner region of the device die. The first portion has a first thickness. The second portion has a second thickness greater than the first thickness.

公开(公告)号：US20230395564A1

公开(公告)日：2023-12-07

申请号：US18446051

申请日：2023-08-08

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Kuan-Yu Huang ,  Li-Chung Kuo ,  Sung-Hui Huang ,  Shang-Yun Hou

IPC: H01L25/065 ,  H01L23/498 ,  H01L25/00 ,  H01L23/31 ,  H01L23/00

CPC classification number: H01L25/0655 ,  H01L23/49833 ,  H01L25/50 ,  H01L23/3185 ,  H01L24/32 ,  H01L24/73 ,  H01L24/33 ,  H01L24/92 ,  H01L25/18

Abstract: A method includes bonding a first package component over a second package component, dispensing a first underfill between the first package component and the second package component, and bonding a third package component over the second package component. A second underfill is between the third package component and the second package component. The first underfill and the second underfill are different types of underfills.

公开(公告)号：US20230387058A1

公开(公告)日：2023-11-30

申请号：US18446732

申请日：2023-08-09

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Kuan-Yu Huang ,  Sung-Hui Huang ,  Shang-Yun Hou ,  Shu Chia Hsu ,  Yu-Yun Huang ,  Wen-Yao Chang ,  Yu-Jen Cheng

IPC: H01L23/00 ,  H01L23/31 ,  H01L23/498 ,  H01L25/065 ,  H01L25/00 ,  H01L21/48 ,  H01L21/56 ,  H01L21/683

CPC classification number: H01L24/17 ,  H01L23/3128 ,  H01L23/49827 ,  H01L25/0655 ,  H01L24/80 ,  H01L23/49838 ,  H01L23/3135 ,  H01L25/50 ,  H01L21/486 ,  H01L24/08 ,  H01L21/565 ,  H01L23/562 ,  H01L21/563 ,  H01L21/6835 ,  H01L24/16 ,  H01L21/4853 ,  H01L2924/3511 ,  H01L2224/08225 ,  H01L2221/68331 ,  H01L2224/80896 ,  H01L2224/16227 ,  H01L2224/17517 ,  H01L2224/80895

Abstract: In an embodiment, an interposer has a first side, a first integrated circuit device attached to the first side of the interposer with a first set of conductive connectors, each of the first set of conductive connectors having a first height, a first die package attached to the first side of the interposer with a second set of conductive connectors, the second set of conductive connectors including a first conductive connector and a second conductive connector, the first conductive connector having a second height, the second conductive connector having a third height, the third height being different than the second height, a first dummy conductive connector being between the first side of the interposer and the first die package, an underfill disposed beneath the first integrated circuit device and the first die package, and an encapsulant disposed around the first integrated circuit device and the first die package.

公开(公告)号：US11621205B2

公开(公告)日：2023-04-04

申请号：US17208694

申请日：2021-03-22

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Yu-Wei Chen ,  Li-Chung Kuo ,  Ying-Ching Shih ,  Szu-Wei Lu ,  Jing-Cheng Lin ,  Long Hua Lee ,  Kuan-Yu Huang

IPC: H01L23/31 ,  H01L23/498 ,  H01L21/56 ,  H01L23/00 ,  H01L25/065

Abstract: A method for forming an underfill structure and semiconductor packages including the underfill structure are disclosed. In an embodiment, the semiconductor package may include a package including an integrated circuit die; an interposer bonded to the integrated circuit die by a plurality of die connectors; and an encapsulant surrounding the integrated circuit die. The semiconductor package may further include a package substrate bonded to the interposer by a plurality of conductive connectors; a first underfill between the package and the package substrate, the first underfill having a first coefficient of thermal expansion (CTE); and a second underfill surrounding the first underfill, the second underfill having a second CTE less than the first CTE.

公开(公告)号：US11569156B2

公开(公告)日：2023-01-31

申请号：US16798404

申请日：2020-02-23

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Kuan-Yu Huang ,  Sung-Hui Huang ,  Shang-Yun Hou

IPC: H01L23/498 ,  H01L21/48 ,  H01L23/053 ,  H01L23/00 ,  H01L23/538

Abstract: A semiconductor device includes a circuit substrate, a semiconductor package, connective terminals and supports. The circuit substrate has a first side and a second side opposite to the first side. The semiconductor package is connected to the first side of the circuit substrate. The connective terminals are located on the second side of the circuit substrate and are electrically connected to the semiconductor package via the circuit substrate. The supports are located on the second side of the circuit substrate beside the connective terminals. A material of the supports has a melting temperature higher than a melting temperature of the connective terminals.

公开(公告)号：US20230014813A1

公开(公告)日：2023-01-19

申请号：US17952681

申请日：2022-09-26

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Chen-Hua Yu ,  Hsing-Kuo Hsia ,  Sung-Hui Huang ,  Kuan-Yu Huang ,  Kuo-Chiang Ting ,  Shang-Yun Hou ,  Chi-Hsi Wu

IPC: G02B6/42 ,  H01L23/00

Abstract: A structure including a photonic integrated circuit die, an electric integrated circuit die, a semiconductor dam, and an insulating encapsulant is provided. The photonic integrated circuit die includes an optical input/output portion and a groove located in proximity of the optical input/output portion, wherein the groove is adapted for lateral insertion of at least one optical fiber. The electric integrated circuit die is disposed over and electrically connected to the photonic integrated circuit die. The semiconductor dam is disposed over the photonic integrated circuit die. The insulating encapsulant is disposed over the photonic integrated circuit die and laterally encapsulates the electric integrated circuit die and the semiconductor dam.

公开(公告)号：US20220367413A1

公开(公告)日：2022-11-17

申请号：US17383911

申请日：2021-07-23

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Kuan-Yu Huang ,  Li-Chung Kuo ,  Sung-Hui Huang ,  Shang-Yun Hou

IPC: H01L25/065 ,  H01L23/00 ,  H01L23/498 ,  H01L25/00 ,  H01L23/31

Abstract: A method includes bonding a first package component over a second package component, dispensing a first underfill between the first package component and the second package component, and bonding a third package component over the second package component. A second underfill is between the third package component and the second package component. The first underfill and the second underfill are different types of underfills.