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    Memory cell with magnetic access selector apparatus
    35.
    发明授权
    Memory cell with magnetic access selector apparatus 有权

    公开(公告)号：US11380840B2

    公开(公告)日：2022-07-05

    申请号：US16824862

    申请日：2020-03-20

    Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

    Inventor： Mauricio Manfrini

    IPC: H01L43/08 ,  H01L27/22 ,  H01L43/02

    Abstract: An integrated chip has a memory cell that includes a magnetic tunnel junction (MTJ) device and an access selector apparatus. The MTJ device includes a free layer and a pinned layer. The access selector apparatus includes a first metal structure and a second metal structure separated by one or more non-metallic layers. The first metal structure includes a polarized magnetic layer. The polarized magnetic layer produces a magnetic field that extends through the free layer, tilting its magnetic field and thereby substantially reducing a switching time for the MTJ device. The access selector apparatus may be a bipolar selector. The polarized magnetic layer may be incorporated into an electrode of the bipolar selector. Both the access selector apparatus and the MTJ device may be formed by a stack of material layers. The resulting memory cell may be compact and have good write speed.

    High-density 3D-dram cell with scaled capacitors
    36.
    发明授权
    High-density 3D-dram cell with scaled capacitors 有权

    公开(公告)号：US11355496B2

    公开(公告)日：2022-06-07

    申请号：US17086628

    申请日：2020-11-02

    Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

    Inventor： Mauricio Manfrini ,  Chung-Te Lin

    IPC: H01L27/108

    Abstract: A semiconductor device comprises a semiconductor substrate, and a pair of metal gates extends upwards from the semiconductor substrate. First and second channel regions are disposed between inner sidewalls of the pair of metal gates. First and second drain regions are disposed between the inner sidewalls of the pair of metal gates and are disposed directly over the first and second channel regions, respectively. First and second source regions are disposed between the inner sidewalls of the pair of metal gates directly below the first and second channel regions, respectively. A capacitor dielectric structure is disposed below the first and second source regions. A bottom capacitor electrode is disposed below the capacitor dielectric. The capacitor dielectric structure separates the first and second drain regions from the bottom capacitor electrode.

    SEMICONDUCTOR DEVICE AND METHOD OF FABRICATING THE SAME
    37.
    发明申请
    SEMICONDUCTOR DEVICE AND METHOD OF FABRICATING THE SAME 有权

    公开(公告)号：US20210391469A1

    公开(公告)日：2021-12-16

    申请号：US16901004

    申请日：2020-06-15

    Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

    Inventor： Gerben Doornbos ,  Blandine Duriez ,  Georgios Vellianitis ,  Marcus Johannes Henricus Van Dal ,  Mauricio Manfrini

    IPC: H01L29/78 ,  H01L27/1159 ,  H01L27/11587 ,  H01L29/66

    Abstract: A semiconductor device includes a semiconductor substrate, a first source region, a first drain region, a first gate, a second source region, a second drain region, a second gate, and a first dielectric layer. The first source region and the first drain region are disposed within the semiconductor substrate. The first gate is disposed over the semiconductor substrate in between the first source region and the first drain region. The second source region and the second drain region are disposed within the semiconductor substrate. The second gate is disposed over the semiconductor substrate in between the second source region and the second drain region. The first dielectric layer is located in between the first gate and the semiconductor substrate, and in between the second gate and the semiconductor substrate, wherein the first dielectric layer extends from a position below the first gate to a position below the second gate.

    MEMORY CELL WITH UNIPOLAR SELECTORS
    38.
    发明申请
    MEMORY CELL WITH UNIPOLAR SELECTORS 有权

    公开(公告)号：US20210043683A1

    公开(公告)日：2021-02-11

    申请号：US16531482

    申请日：2019-08-05

    Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

    Inventor： Katherine H. Chiang ,  Chung-Te Lin ,  Mauricio Manfrini

    IPC: H01L27/22 ,  G11C11/16 ,  H01L43/02 ,  H01L43/12

    Abstract: In some embodiments, the present disclosure relates to an integrated circuit. The integrated circuit has a magnetic tunnel junction (MTJ) device disposed within a dielectric structure over a substrate. The MTJ device has a MTJ disposed between a first electrode and a second electrode. A first unipolar selector is disposed within the dielectric structure and is coupled to the first electrode. The first unipolar selector is configured to allow current to flow through the MTJ device along a first direction. A second unipolar selector is disposed within the dielectric structure and is coupled to the first electrode. The second unipolar selector is configured to allow current to flow through the MTJ device along a second direction opposite the first direction.

    METAL FILAMENT VIAS FOR INTERCONNECT STRUCTURE
    40.
    发明申请
    METAL FILAMENT VIAS FOR INTERCONNECT STRUCTURE 审中-公开

    公开(公告)号：US20200176379A1

    公开(公告)日：2020-06-04

    申请号：US16525978

    申请日：2019-07-30

    Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

    Inventor： Mauricio Manfrini ,  Marcus Johannes Henricus van Dal

    IPC: H01L23/522 ,  H01L23/532 ,  H01L21/768

    Abstract: The present disclosure relates to an integrated chip including a filament via. In some embodiments, a lower metal layer is disposed over a substrate. A filament dielectric layer is disposed over the lower metal layer. An upper metal layer is disposed over the filament dielectric layer. A filament via is disposed through the filament dielectric layer and electrically connecting the lower metal layer and the upper metal layer. The filament via may be established after other steps of forming the integration chip are finished, therefore making possible barrier-less Cu vias at scaled dimensions. Using the disclosed methods, ultra-scaled vias (e.g. down to 1 nm) can be achieved due to intrinsic character of filament formation mechanism.

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