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    SEMICONDUCTOR DEVICE, METHOD OF MANUFACTURING SAME AND METHOD OF DESIGNING SAME
    31.
    发明申请
    SEMICONDUCTOR DEVICE, METHOD OF MANUFACTURING SAME AND METHOD OF DESIGNING SAME 有权
    半导体器件，其制造方法和设计方法

    公开(公告)号：US20080315313A1

    公开(公告)日：2008-12-25

    申请号：US11866693

    申请日：2007-10-03

    申请人： Yasuo YAMAGUCHI ,  Shigeto Maegawa ,  Takashi Ipposhi ,  Toshiaki Iwamatsu ,  Shigenobu Maeda ,  Yuuichi Hirano ,  Takuji Matsumoto ,  Shoichi Miyamoto

    发明人： Yasuo YAMAGUCHI ,  Shigeto Maegawa ,  Takashi Ipposhi ,  Toshiaki Iwamatsu ,  Shigenobu Maeda ,  Yuuichi Hirano ,  Takuji Matsumoto ,  Shoichi Miyamoto

    IPC分类号： H01L27/12

    CPC分类号： H01L21/84 ,  H01L27/1203

    摘要： A partial oxide film with well regions formed therebeneath isolates transistor formation regions in an SOI layer from each other. A p-type well region is formed beneath part of the partial oxide film which isolates NMOS transistors from each other, and an n-type well region is formed beneath part of the partial oxide film which isolates PMOS transistors from each other. The p-type well region and the n-type well region are formed in side-by-side relation beneath part of the partial oxide film which provides isolation between the NMOS and PMOS transistors. A body region is in contact with the well region adjacent thereto. An interconnect layer formed on an interlayer insulation film is electrically connected to the body region through a body contact provided in the interlayer insulation film. A semiconductor device having an SOI structure reduces a floating-substrate effect.

    摘要翻译： 在其之间形成的具有阱区的部分氧化膜彼此隔离SOI层中的晶体管形成区域。 在部分氧化膜的下部形成有p型阱区，其将NMOS晶体管彼此隔离，并且在部分氧化膜的下部形成n型阱区，其将PMOS晶体管彼此隔离。 p型阱区域和n型阱区域在部分氧化膜的一部分下方并排地形成，其提供NMOS和PMOS晶体管之间的隔离。 身体区域与与其相邻的井区域接触。 形成在层间绝缘膜上的互连层通过设置在层间绝缘膜中的体接触电连接到体区。 具有SOI结构的半导体器件减少浮置衬底效应。

    Semiconductor memory device and method of manufacturing the same
    33.
    发明授权
    Semiconductor memory device and method of manufacturing the same 失效
    半导体存储器件及其制造方法

    公开(公告)号：US07271454B2

    公开(公告)日：2007-09-18

    申请号：US10927638

    申请日：2004-08-27

    申请人： Yuuichi Hirano ,  Takashi Ipposhi ,  Shigeto Maegawa ,  Koji Nii

    发明人： Yuuichi Hirano ,  Takashi Ipposhi ,  Shigeto Maegawa ,  Koji Nii

    IPC分类号： H01L29/76 ,  H01L29/94 ,  H01L31/00

    CPC分类号： H01L21/84 ,  H01L27/0207 ,  H01L27/11 ,  H01L27/1108 ,  H01L27/1203 ,  Y10S257/903 ,  Y10S257/904

    摘要： A contact connected to a word line is formed on a gate electrode of an access transistor of an SRAM cell. The contact passes through an element isolation insulating film to reach an SOI layer. A body region of a driver transistor and that of the access transistor are electrically connected with each other through the SOI layer located under the element isolation insulating film. Therefore, the access transistor is in a DTMOS structure having the gate electrode connected with the body region through the contact, which in turn is also electrically connected to the body region of the driver transistor. Thus, operations can be stabilized while suppressing increase of an area for forming the SRAM cell.

    摘要翻译： 连接到字线的触点形成在SRAM单元的存取晶体管的栅电极上。 接触通过元件隔离绝缘膜以达到SOI层。 驱动晶体管的体区和存取晶体管的体区通过位于元件隔离绝缘膜下方的SOI层彼此电连接。 因此，存取晶体管是具有通过触点与主体区域连接的栅电极的DTMOS结构，该触点又电连接到驱动晶体管的体区。 因此，可以在抑制用于形成SRAM单元的区域的增加的同时稳定操作。

    Semiconductor device including high frequency circuit with inductor
    36.
    发明授权
    Semiconductor device including high frequency circuit with inductor 有权
    半导体器件包括带电感的高频电路

    公开(公告)号：US06727572B2

    公开(公告)日：2004-04-27

    申请号：US10340664

    申请日：2003-01-13

    申请人： Shigenobu Maeda ,  Shigeto Maegawa ,  Takashi Ipposhi ,  Toshiaki Iwamatsu

    发明人： Shigenobu Maeda ,  Shigeto Maegawa ,  Takashi Ipposhi ,  Toshiaki Iwamatsu

    IPC分类号： H01L2900

    CPC分类号： H01L23/645 ,  H01L21/84 ,  H01L23/522 ,  H01L23/5227 ,  H01L27/0688 ,  H01L27/1203 ,  H01L28/10 ,  H01L2924/0002 ,  H01L2924/00

    摘要： A semiconductor device with a spiral inductor is provided, which determines the area of an insulation layer to be provided in the surface of a wiring board thereunder. A trench isolation oxide film, which is a complete isolation oxide film including in part the structure of a partial isolation oxide film, is provided in a larger area of the surface of an SOI layer than that corresponding to the area of a spiral inductor. The trench isolation oxide film includes a first portion having a first width and extending in a direction approximately perpendicular the surface of a buried oxide film, and a second portion having a second width smaller than the first width and being continuously formed under the first portion, extending approximately perpendicular to the surface of the buried oxide film. The trench isolation oxide film is provided such that a horizontal distance between each end surface of the second portion and a corresponding end surface of the spiral inductor makes a predetermined distance or more.

    摘要翻译： 提供具有螺旋电感器的半导体器件，其确定要在其下面的布线板的表面中提供的绝缘层的面积。 在SOI层表面的与螺旋形电感器的面积相对应的面的大面积上，设置有作为部分隔离氧化膜的结构的完全隔离氧化膜的沟槽隔离氧化膜。 沟槽隔离氧化膜包括具有第一宽度并且在大致垂直于掩埋氧化膜的表面的方向上延伸的第一部分和具有小于第一宽度的第二宽度的第二部分并且连续地形成在第一部分下方， 大致垂直于埋入氧化膜的表面延伸。 沟槽隔离氧化膜被设置为使得第二部分的每个端表面与螺旋电感器的相应端面之间的水平距离达到预定距离或更大。

    Semiconductor device having a thin film transistor and manufacturing method thereof
    37.
    发明授权
    Semiconductor device having a thin film transistor and manufacturing method thereof 失效
    具有薄膜晶体管的半导体器件及其制造方法

    公开(公告)号：US06693324B2

    公开(公告)日：2004-02-17

    申请号：US08709071

    申请日：1996-09-06

    申请人： Shigeto Maegawa ,  Takashi Ipposhi ,  Toshiaki Iwamatsu

    发明人： Shigeto Maegawa ,  Takashi Ipposhi ,  Toshiaki Iwamatsu

    IPC分类号： H01L2701

    CPC分类号： H01L29/785 ,  H01L21/28008 ,  H01L29/42392 ,  H01L29/66757 ,  H01L29/66795 ,  H01L29/78618

    摘要： A semiconductor layer has one end placed on top of a first conductive layer and in contact with the first conductive layer, and the other end placed on top of a second conductive layer and in contact with the second conductive layer. At the central portion, the semiconductor layer faces a gate electrode layer with a gate insulating layer interposed therebetween. The semiconductor layer is formed so that its width W1 is smaller than its height H1. As a result, a thin film transistor and manufacturing method thereof can be obtained in which contact between a source/drain region of the thin film transistor and an upper or lower conductive layer can be made stably.

    摘要翻译： 半导体层的一端放置在第一导电层的顶部并与第一导电层接触，另一端放置在第二导电层的顶部并与第二导电层接触。 在中心部分，半导体层面对栅极电极层，其间具有栅极绝缘层。 形成半导体层，使得其宽度W1小于其高度H1。 结果，可以获得薄膜晶体管及其制造方法，其中可以稳定地制造薄膜晶体管的源/漏区与上或下导电层之间的接触。

    Semiconductor device and manufacturing method for the same
    40.
    发明授权
    Semiconductor device and manufacturing method for the same 有权
    半导体器件及其制造方法相同

    公开(公告)号：US08350331B2

    公开(公告)日：2013-01-08

    申请号：US11627167

    申请日：2007-01-25

    申请人： Mikio Tsujiuchi ,  Toshiaki Iwamatsu ,  Shigeto Maegawa

    发明人： Mikio Tsujiuchi ,  Toshiaki Iwamatsu ,  Shigeto Maegawa

    IPC分类号： H01L21/70

    CPC分类号： H01L27/1203 ,  H01L21/84

    摘要： In a semiconductor device, a body thick film transistor and a body thin film transistor having a different body film thickness are formed on the same SOI substrate (silicon support substrate, buried oxide film and silicon layer). The body film is formed to be relatively thick in the body thick film transistor, which has a recess structure where the level of the surface of the source/drain regions is lower than the level of the surface of the body region, and thus, the SOI film in the source/drain regions is formed to be as thin as the SOI film in the body thin film transistor. On the other hand, the entirety of the SOI film is formed to have a relatively thin film thickness in the body thin film transistor. In addition, the source/drain regions are formed to penetrate through the silicon layer.

    摘要翻译： 在半导体器件中，在相同的SOI衬底（硅支撑衬底，掩埋氧化物膜和硅层）上形成具有不同体膜厚度的体积薄膜晶体管和体薄膜晶体管。 体膜形成为比较厚的体膜厚晶体管，其具有凹陷结构，其中源/漏区的表面的水平低于体区的表面的水平，因此， 源极/漏极区域中的SOI膜形成为与体薄膜晶体管中的SOI膜一样薄。 另一方面，在体薄膜晶体管中，整个SOI膜形成为具有较薄的膜厚。 此外，源极/漏极区域形成为穿透硅层。