公开(公告)号：US06548344B1

公开(公告)日：2003-04-15

申请号：US09987956

申请日：2001-11-16

申请人： Jochen Beintner ,  Stephan Kudelka ,  Thomas Dyer

发明人： Jochen Beintner ,  Stephan Kudelka ,  Thomas Dyer

IPC分类号： H01L218242

CPC分类号： H01L27/10864 ,  H01L27/10888 ,  H01L27/10891

摘要： In the formation of a semiconductor structure, where spacer formation is strongly dependent on the structure (e.g. taper), the improvement of a spacer formation on a poly stud planarized to pad nitride where an oxide is formed on top of the poly prior to the pad nitride strip, so that after pad nitride removal, the poly is etched back and nitride is deposited conformal followed by anisotropic nitride RIE etch, so that the oxide protects the nitride underneath from being etched.

摘要翻译： 在半导体结构的形成中，其中间隔物形成强烈地取决于结构（例如锥形），改善在平坦化为衬垫氮化物的多晶硅柱上的间隔物形成，其中在衬垫之前在聚氨酯的顶部上形成氧化物 氮化物条，使得在去除衬垫氮化物之后，将多晶硅回蚀刻，并且将氮化物保形共形，随后进行各向异性氮化物RIE蚀刻，使得氧化物保护下方的氮化物免受蚀刻。

公开(公告)号：US20080111202A1

公开(公告)日：2008-05-15

申请号：US12013622

申请日：2008-01-14

申请人： Thomas Dyer ,  Sunfei Fang ,  Jiang Yan

发明人： Thomas Dyer ,  Sunfei Fang ,  Jiang Yan

IPC分类号： H01L29/78

CPC分类号： H01L21/823871 ,  H01L21/76895 ,  H01L21/76897 ,  H01L21/823864 ,  H01L29/665 ,  H01L29/6653 ,  H01L29/6659 ,  H01L29/7843

摘要： Embodiments of the present invention provide a method of forming a conductive stud contacting a semiconductor device. The method includes forming a protective layer covering the semiconductor device; selectively etching an opening down through the protective layer reaching a contact area of the semiconductor device, the opening being away from a protected area of the semiconductor device; and filling the opening with a conductive material to form the conductive stud. One embodiment may further include forming a dielectric liner directly on top of the semiconductor device, and forming the protective layer on top of the dielectric liner. Embodiments of the present invention also provide a semiconductor device made thereof.

公开(公告)号：US20070254420A1

公开(公告)日：2007-11-01

申请号：US11380743

申请日：2006-04-28

申请人： Atul Ajmera ,  Christopher Baiocco ,  Xiangdong Chen ,  Thomas Dyer ,  Sunfei Fang ,  Wenzhi Gao

发明人： Atul Ajmera ,  Christopher Baiocco ,  Xiangdong Chen ,  Thomas Dyer ,  Sunfei Fang ,  Wenzhi Gao

IPC分类号： H01L21/338 ,  H01L21/20 ,  H01L29/76

CPC分类号： H01L21/823425 ,  H01L21/823412 ,  H01L21/823468 ,  H01L21/823807 ,  H01L21/823864 ,  H01L29/6653 ,  H01L29/6656 ,  H01L29/6659 ,  H01L29/7843

摘要： Methods for source/drain implantation and strain transfer to a channel of a semiconductor device and a related semiconductor device are disclosed. In one embodiment, the method includes using a first size spacer for deep source/drain implantation adjacent a gate region of a semiconductor device; and using a second, smaller size spacer for silicide formation adjacent the gate region and transferring strain from a stress liner to a channel underlying the gate region. One embodiment of a semiconductor device may include a gate region atop a substrate; a spacer including a spacer core and an outer spacer member about the spacer core; a deep source/drain region within the substrate and distanced from the spacer; and a silicide region within the substrate and overlapping and extending beyond the deep source/drain region, the silicide region aligned to the spacer.

摘要翻译： 公开了用于源极/漏极注入和应变转移到半导体器件和相关半导体器件的沟道的方法。 在一个实施例中，该方法包括使用与半导体器件的栅极区域相邻的深源极/漏极注入的第一尺寸间隔物; 并且使用第二较小尺寸的间隔物，用于邻近栅极区域的硅化物形成，并将应变从应力衬垫转移到栅极区域下方的沟道。 半导体器件的一个实施例可以包括位于衬底顶部的栅极区域; 间隔件，其包括间隔件芯和围绕所述间隔件芯的外部间隔件; 衬底内的深源极/漏极区域，并远离间隔物; 以及衬底内的硅化物区域，并且重叠并延伸超过深源极/漏极区域，硅化物区域与间隔物对准。

公开(公告)号：US20070254412A1

公开(公告)日：2007-11-01

申请号：US11380692

申请日：2006-04-28

申请人： Thomas Dyer ,  Haining Yang

发明人： Thomas Dyer ,  Haining Yang

IPC分类号： H01L21/8232 ,  H01L29/76

CPC分类号： H01L21/823807 ,  H01L21/823821 ,  H01L27/0922 ,  H01L27/1211 ,  H01L29/04 ,  H01L29/66795 ,  H01L29/7853

摘要： The present invention relates to high performance three-dimensional (3D) field effect transistors (FETs). Specifically, a 3D semiconductor structure having a bottom surface oriented along one of a first set of equivalent crystal planes and multiple additional surfaces oriented along a second, different set of equivalent crystal planes can be used to form a high performance 3D FET with carrier channels oriented along the second, different set of equivalent crystal planes. More importantly, such a 3D semiconductor structure can be readily formed over the same substrate with an additional 3D semiconductor structure having a bottom surface and multiple additional surfaces all oriented along the first set of equivalent crystal planes. The additional 3D semiconductor structure can be used to form an additional 3D FET, which is complementary to the above-described 3D FET and has carrier channels oriented along the first set of equivalent crystal planes.

公开(公告)号：US20070072429A1

公开(公告)日：2007-03-29

申请号：US11162800

申请日：2005-09-23

申请人： Thomas Dyer ,  Kenneth Settlemyer ,  James Toomey ,  Haining Yang

发明人： Thomas Dyer ,  Kenneth Settlemyer ,  James Toomey ,  Haining Yang

IPC分类号： C23F1/00 ,  H01L21/311 ,  H01L21/302 ,  B44C1/22

CPC分类号： H01L21/30608 ,  H01L21/32134

摘要： A method for producing predetermined shapes in a crystalline Si-containing material that have substantially uniform straight sides or edges and well-defined inside and outside corners is provided together with the structure that is formed utilizing the method of the present invention. The inventive method utilizes conventional photolithography and etching to transfer a pattern, i.e., shape, to a crystalline Si-containing material. Since conventional processing is used, the patterns have the inherent limitations of rounded corners. A selective etching process utilizing a solution of diluted ammonium hydroxide is used to eliminate the rounded corners providing a final shape that has substantially straight sides or edges and substantially rounded corners.

摘要翻译： 与使用本发明的方法形成的结构一起设置在具有基本上均匀的直边或边缘以及明确限定的内角和外角的含Si结晶材料中产生预定形状的方法。 本发明的方法利用常规的光刻和蚀刻将图案（即形状）转移到含结晶的含Si材料。 由于使用了常规处理，所以图案具有圆角的固有限制。 使用利用稀释氢氧化铵溶液的选择性蚀刻方法来消除圆角，提供具有基本上直的边或边缘和基本上圆角的最终形状。

公开(公告)号：US20050133846A1

公开(公告)日：2005-06-23

申请号：US10741203

申请日：2003-12-19

申请人： Thomas Dyer ,  Chun-Yung Sung ,  Ravikumar Ramachandran ,  Ramachandra Divakaruni

发明人： Thomas Dyer ,  Chun-Yung Sung ,  Ravikumar Ramachandran ,  Ramachandra Divakaruni

IPC分类号： H01L21/8242 ,  H01L29/94 ,  H01L27/108 ,  H01L31/119

CPC分类号： H01L27/1087 ,  H01L29/945

摘要： A deep trench capacitor used in a trench DRAM includes a buried plate and an isolation collar. The deep trench is bottle-shaped, and the isolation collar is formed in upper portion of the wider region of the bottle-shaped trench. The buried plate surrounds the lower portion of the wider part of the bottle-shaped trench, and hemispherical grain polysilicon lines the walls of at least the lower portion of the wider part of the trench. A nitride liner layer lines the inner walls of the oxide collar and prevents diffusion of dopant through the oxide collar into the substrate when the HSG polysilicon and the doped buried plate are formed. The buried plate region is self-aligned to the isolation collar. The depth of the top of the wider part of the bottle shape and the bottom depth of the isolation collar are determined by successive resist deposition and recessing steps.

摘要翻译： 在沟槽DRAM中使用的深沟槽电容器包括掩埋板和隔离环。 深沟是瓶形的，并且隔离套环形成在瓶形沟槽的较宽区域的上部。 掩埋板围绕瓶形沟槽的较宽部分的下部，半球状晶粒多晶硅线路至少沟槽较宽部分的下部的壁。 当形成HSG多晶硅和掺杂掩埋板时，氮化物衬垫层线化氧化物环的内壁并防止掺杂剂通过氧化物环到衬底中的扩散。 掩埋板区域与隔离套环自对准。 通过连续的抗蚀剂沉积和凹陷步骤确定瓶子形状的较宽部分的顶部的深度和隔离环的底部深度。