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    Power semiconductor device
    31.
    发明授权
    Power semiconductor device 失效
    功率半导体器件

    公开(公告)号：US5714775A

    公开(公告)日：1998-02-03

    申请号：US633688

    申请日：1996-04-19

    申请人： Tomoki Inoue ,  Ichiro Omura ,  Hiromichi Ohashi

    发明人： Tomoki Inoue ,  Ichiro Omura ,  Hiromichi Ohashi

    IPC分类号： H01L29/06 ,  H01L29/10 ,  H01L29/32 ,  H01L29/739 ,  H01L29/74 ,  H01L31/111

    CPC分类号： H01L29/7397 ,  H01L29/0696 ,  H01L29/1095 ,  H01L29/32

    摘要： A p-type emitter layer having a low resistivity is arranged on a bottom surface of an n-type base layer having a high resistivity. A p-type base layer is formed in a top surface of the n-type base layer. Trenches are formed in the p-type base layer and the n-type base layer such that each trench penetrates the p-type base layer and reaches down to a halfway depth in the n-type base layer. Inter-trench regions made of semiconductor are defined between the trenches. An n-type emitter layer having a low resistivity is formed in a surface of the p-type base layer to be in contact with the upper part of each trench. A gate electrode is buried via a gate insulating film in each trench. That side surface of each inter-trench region which faces the gate electrode consists of a {100} plane.

    摘要翻译： 具有低电阻率的p型发射极层布置在具有高电阻率的n型基极层的底表面上。 p型基底层形成在n型基底层的顶表面上。 在p型基底层和n型基底层中形成沟槽，使得每个沟槽穿过p型基底层并在n型基底层中下降到中间深度。 在沟槽之间限定由半导体制成的沟槽间区域。 在p型基底层的表面上形成具有低电阻率的n型发射极层，以与每个沟槽的上部接触。 每个沟槽中的栅极绝缘膜埋入栅电极。 面对栅电极的每个沟槽间区域的侧表面由{100}平面组成。

    Insulated-gate semiconductor device
    32.
    发明授权
    Insulated-gate semiconductor device 失效
    绝缘栅半导体器件

    公开(公告)号：US5689121A

    公开(公告)日：1997-11-18

    申请号：US480389

    申请日：1995-06-07

    申请人： Mitsuhiko Kitagawa ,  Ichiro Omura ,  Akio Nakagawa ,  Norio Yasuhara ,  Tomoki Inoue

    发明人： Mitsuhiko Kitagawa ,  Ichiro Omura ,  Akio Nakagawa ,  Norio Yasuhara ,  Tomoki Inoue

    IPC分类号： H01L29/06 ,  H01L29/423 ,  H01L29/739 ,  H01L29/745 ,  H01L29/74 ,  H01L31/111

    CPC分类号： H01L29/7455 ,  H01L29/7394 ,  H01L29/7397 ,  H01L29/7398 ,  H01L29/0696 ,  H01L29/4236

    摘要： An insulated-gate semiconductor device comprises a P type emitter layer, an N.sup.- high-resistive base layer formed on the P type emitter layer, and a P type base layer contacting the N.sup.- high-resistive base layer. A plurality of trenches are formed having a depth to reach into the N.sup.- high-resistive base layer from the P type base layer. A gate electrode covered with a gate insulation film is buried in each trench. An N type source layer to be connected to a cathode electrode is formed in the surface of the P type base layer in a channel region between some trenches, thereby forming an N channel MOS transistor for turn-on operation. A P channel MOS transistor connected to the P base layer is formed in a channel region between other trenches so as to discharge the holes outside the device upon turn-off operation.

    摘要翻译： 绝缘栅半导体器件包括P型发射极层，形成在P型发射极层上的N-高电阻基极层和与N型高电阻基极层接触的P型基极层。 形成从P型基底层到达N个高电阻基底层的深度的多个沟槽。 覆盖有栅极绝缘膜的栅电极被埋在每个沟槽中。 在一些沟槽之间的沟道区域中，在P型基极层的表面形成有与阴极连接的N型源极层，从而形成用于导通工作的N沟道MOS晶体管。 连接到P基极层的P沟道MOS晶体管形成在其它沟槽之间的沟道区域中，以便在关断操作时将器件的孔排出。

    Solid-state imaging device including three stacked photoelectric conversion layers, three accumulators, and a single readout circuit
    33.
    发明授权
    Solid-state imaging device including three stacked photoelectric conversion layers, three accumulators, and a single readout circuit 失效
    固态成像装置包括三个堆叠的光电转换层，三个累加器和单个读出电路

    公开(公告)号：US07932942B2

    公开(公告)日：2011-04-26

    申请号：US11353236

    申请日：2006-02-14

    申请人： Tomoki Inoue ,  Atsuhiko Ishihara

    发明人： Tomoki Inoue ,  Atsuhiko Ishihara

    IPC分类号： H04N3/14 ,  H01L27/146

    CPC分类号： H04N9/045 ,  H04N2209/047

    摘要： A solid-state imaging device is provided and has: three photoelectric conversion layers stacked above a semiconductor substrate 1, each detecting a different color; three signal charge accumulators in a semiconductor substrate for accumulating signal charges generated in each of the three photoelectric conversion layers: and a signal readout circuit in the semiconductor substrate for reading out signals corresponding to the signal charges accumulated in the signal charge accumulators. The three signal charge accumulators are arranged in a direction in the surface of the semiconductor substrate as a pixel and a plurality of the pixels are arranged in a square lattice pattern both in the direction and a direction perpendicular thereto. The three signal charge accumulators arranged in each pixel in an odd row are arranged such that an array of the signal charge accumulators in the first sub-row of each pixel has all of the three signal charge accumulators.

    摘要翻译： 提供了一种固态成像装置，具有：叠层在半导体基板1上的三个光电转换层，每个检测不同的颜色; 用于累积在三个光电转换层中的每一个中产生的信号电荷的半导体衬底中的三个信号电荷累加器和用于读出与累积在信号电荷累加器中的信号电荷相对应的信号的半导体衬底中的信号读出电路。 三个信号电荷累积器沿着半导体衬底的表面的方向作为像素布置，并且多个像素在垂直于其的方向和方向上以正方形的格子图案排列。 布置在奇数行的每个像素中的三个信号电荷累加器布置成使得每个像素的第一子行中的信号电荷累加器的阵列具有三个信号电荷累加器的全部。

    Semiconductor device
    36.
    发明授权
    Semiconductor device 有权
    半导体器件

    公开(公告)号：US07492031B2

    公开(公告)日：2009-02-17

    申请号：US11434185

    申请日：2006-05-16

    申请人： Koichi Sugiyama ,  Tomoki Inoue ,  Hideaki Ninomiya ,  Masakazu Yamaguchi

    发明人： Koichi Sugiyama ,  Tomoki Inoue ,  Hideaki Ninomiya ,  Masakazu Yamaguchi

    IPC分类号： H01L29/00

    CPC分类号： H01L29/7397 ,  H01L29/4232 ,  H01L29/42372 ,  H01L29/7395

    摘要： A semiconductor device comprises a first base layer of a first conductive type which has a first surface and a second surface; a second base layer of a second conductive type which is formed on the first surface; first and second gate electrodes which are formed by embedding an electrically conductive material into a plurality of trenches via gate insulating films, the plurality of trenches being formed such that bottoms of the trenches reach the first base layer; source layers of the first conductive type which are formed on a surface area of the second base layer so as to be adjacent to both side walls of the trench provided with the first gate electrode and one side wall of the trench provided with the second gate electrode, respectively; an emitter layer of the second conductive type which is formed on the second surface; emitter electrodes which are formed on the second base layer and the source layers; a collector electrode which is formed on the emitter layer; and first and second terminals which are electrically connected to the first and second gate electrodes, respectively.

    摘要翻译： 半导体器件包括具有第一表面和第二表面的第一导电类型的第一基底层; 形成在第一表面上的第二导电类型的第二基层; 通过经由栅极绝缘膜将导电材料嵌入多个沟槽而形成的第一和第二栅电极，所述多个沟槽形成为使得沟槽的底部到达第一基底层; 源极层，其形成在第二基极层的表面区域上，以与设置有第一栅电极的沟槽的两个侧壁相邻，并且设置有第二栅电极的沟槽的一个侧壁 ， 分别; 形成在第二表面上的第二导电类型的发射极层; 在第二基极层和源极层上形成的发射极; 在发射极层上形成的集电极; 以及分别电连接到第一和第二栅电极的第一和第二端子。

    Semiconductor Device
    37.
    发明申请
    Semiconductor Device 审中-公开
    半导体器件

    公开(公告)号：US20090039386A1

    公开(公告)日：2009-02-12

    申请号：US12249573

    申请日：2008-10-10

    申请人： Tsuneo OGURA ,  Masakazu Yamaguchi ,  Tomoki Inoue ,  Hideaki Ninomiya ,  Koichi Sugiyama

    发明人： Tsuneo OGURA ,  Masakazu Yamaguchi ,  Tomoki Inoue ,  Hideaki Ninomiya ,  Koichi Sugiyama

    IPC分类号： H01L29/739

    CPC分类号： H01L29/1095 ,  H01L29/0834 ,  H01L29/7397

    摘要： A semiconductor device comprises a first base layer of a first conductivity type; a plurality of second base layers of a second conductivity type, provided on a part of a first surface of the first base layer; trenches formed on each side of the second base layers, and formed to be deeper than the second base layers; an emitter layer formed along the trench on a surface of the second base layers; a collector layer of the second conductivity type, provided on a second surface of the first base layer opposite to the first surface; an insulating film formed on an inner wall of the trench, the insulating film being thicker on a bottom of the trench than on a side surface of the trench; a gate electrode formed within the trench, and isolated from the second base layers and the emitter layer by the insulating film; and a space section provided between the second base layers adjacent to each other, the space section being deeper than the second base layers and being electrically isolated from the emitter layer and the second base layers.

    摘要翻译： 半导体器件包括第一导电类型的第一基极层; 多个第二导电类型的第二基层，设置在所述第一基底层的第一表面的一部分上; 沟槽形成在第二基底层的每一侧上，并且形成为比第二基底层更深; 在所述第二基底层的表面上沿着所述沟槽形成的发射极层; 设置在与第一表面相对的第一基底层的第二表面上的第二导电类型的集电极层; 形成在所述沟槽的内壁上的绝缘膜，所述绝缘膜在所述沟槽的底部比在所述沟槽的侧表面上更厚; 形成在所述沟槽内并与所述第二基极层和所述发射极层通过所述绝缘膜隔离的栅电极; 以及设置在彼此相邻的第二基底层之间的空间部分，空间部分比第二基底层更深，并且与发射极层和第二基底层电隔离。

    Photoelectric converting film stack type solid-state image pickup device and method of producing the same
    38.
    发明授权
    Photoelectric converting film stack type solid-state image pickup device and method of producing the same 失效
    光电转换膜堆叠式固态摄像装置及其制造方法

    公开(公告)号：US07400023B2

    公开(公告)日：2008-07-15

    申请号：US11082901

    申请日：2005-03-18

    申请人： Mikio Watanabe ,  Tomoki Inoue ,  Masafumi Inuiya

    发明人： Mikio Watanabe ,  Tomoki Inoue ,  Masafumi Inuiya

    IPC分类号： H01L31/062

    CPC分类号： H01L27/14647 ,  H01L27/14609 ,  H01L27/14621 ,  H01L27/14687 ,  H01L27/14692

    摘要： In a photoelectric converting film stack type solid-state image pickup device, a plurality of photoelectric converting film are stacked on a semiconductor substrate in which a signal readout circuit is formed, each of the photoelectric converting films is sandwiched between a common electrode film and pixel electrode films corresponding to respective pixels, and photo-charges generated in the photoelectric converting films are taken out through the pixel electrode films. In the solid-state image pickup device, a common electrode film for a first photoelectric converting film is used also as a common electrode film for a second photoelectric converting film, the first photoelectric converting film is stacked below the common electrode film, and the second photoelectric converting film is stacked above the common electrode film.

    摘要翻译： 在光电转换膜堆叠型固态摄像装置中，在形成信号读出电路的半导体基板上层叠多个光电转换膜，将各光电转换膜夹在公共电极膜和像素 对应于各个像素的电极膜和在光电转换膜中产生的光电荷通过像素电极膜被取出。 在固态摄像装置中，第一光电转换膜用公共电极膜也用作第二光电转换膜的公共电极膜，第一光电转换膜堆叠在公共电极膜的下方，第二光电转换膜 光电转换膜层叠在公共电极膜的上方。

    Solid-state imaging device
    39.
    发明申请
    Solid-state imaging device 失效
    固态成像装置

    公开(公告)号：US20080055437A1

    公开(公告)日：2008-03-06

    申请号：US11353236

    申请日：2006-02-14

    申请人： Tomoki Inoue ,  Atsuhiko Ishihara

    发明人： Tomoki Inoue ,  Atsuhiko Ishihara

    IPC分类号： H04N3/14

    CPC分类号： H04N9/045 ,  H04N2209/047

    摘要： A solid-state imaging device is provided and has; three photoelectric conversion layers stacked above a semiconductor substrate 1, each detecting a different color; three signal charge accumulators in a semiconductor substrate for accumulating signal charges generated in each of the three photoelectric conversion layers: and a signal readout circuit in the semiconductor substrate for reading out signals corresponding to the signal charges accumulated in the signal charge accumulators. The three signal charge accumulators are arranged in a direction in the surface of the semiconductor substrate as a pixel and a plurality of the pixels are arranged in a square lattice pattern both in the direction and a direction perpendicular thereto. The three signal charge accumulators arranged in each pixel in an odd row are arranged such that an array of the signal charge accumulators in the first sub-row of each pixel has all of the three signal charge accumulators.

    摘要翻译： 提供固态成像装置，具有： 三个光电转换层堆叠在半导体衬底1上方，每个检测不同的颜色; 用于累积在三个光电转换层中的每一个中产生的信号电荷的半导体衬底中的三个信号电荷累加器和用于读出与累积在信号电荷累加器中的信号电荷相对应的信号的半导体衬底中的信号读出电路。 三个信号电荷累积器沿着半导体衬底的表面的方向作为像素布置，并且多个像素在垂直于其的方向和方向上以正方形的格子图案排列。 布置在奇数行的每个像素中的三个信号电荷累加器布置成使得每个像素的第一子行中的信号电荷累加器的阵列具有三个信号电荷累加器的全部。

    Power semiconductor device
    40.
    发明授权
    Power semiconductor device 有权
    功率半导体器件

    公开(公告)号：US07268390B2

    公开(公告)日：2007-09-11

    申请号：US11102851

    申请日：2005-04-11

    申请人： Tsuneo Ogura ,  Tomoki Inoue ,  Hideaki Ninomiya ,  Koichi Sugiyama

    发明人： Tsuneo Ogura ,  Tomoki Inoue ,  Hideaki Ninomiya ,  Koichi Sugiyama

    IPC分类号： H01L29/76

    CPC分类号： H01L29/1095 ,  H01L29/0619 ,  H01L29/0692 ,  H01L29/0696 ,  H01L29/083 ,  H01L29/0834 ,  H01L29/7394 ,  H01L29/7397

    摘要： A semiconductor device includes a base layer of a first conductivity type, a barrier layer of a first conductivity type formed on the base layer, a trench formed from the surface of the barrier layer to such a depth as to reach a region in the vicinity of an interface between the barrier layer and the base layer, a gate electrode formed in the trench via a gate insulating film, a contact layer of a second conductivity type selectively formed in a surface portion of the barrier layer, a source layer of the first conductivity type selectively formed in the surface portion of the barrier layer so as to contact the contact layer and a side wall of the gate insulating film in the trench, and a first main electrode formed so as to contact the contact layer and the source layer.

    摘要翻译： 半导体器件包括第一导电类型的基底层，形成在基底层上的第一导电类型的阻挡层，从阻挡层的表面形成的沟槽到达达到 阻挡层和基底层之间的界面，通过栅极绝缘膜形成在沟槽中的栅极电极，选择性地形成在阻挡层的表面部分中的第二导电类型的接触层，第一导电性的源极层 形成在所述阻挡层的表面部分中以与所述沟槽中的所述接触层和所述栅极绝缘膜的侧壁接触的第一主电极以及与所述接触层和所述源极层接触的第一主电极。