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114 条记录 (耗时 0.042 秒)

    Semiconductor device
    31.
    发明授权
    Semiconductor device 有权
    半导体器件

    公开(公告)号：US08132063B2

    公开(公告)日：2012-03-06

    申请号：US13191442

    申请日：2011-07-26

    申请人： Motoyasu Terao ,  Satoru Hanzawa ,  Hitoshi Kume ,  Minoru Ogushi ,  Yoshitaka Sasago ,  Masaharu Kinoshita ,  Norikatsu Takaura

    发明人： Motoyasu Terao ,  Satoru Hanzawa ,  Hitoshi Kume ,  Minoru Ogushi ,  Yoshitaka Sasago ,  Masaharu Kinoshita ,  Norikatsu Takaura

    IPC分类号： G11C29/00

    CPC分类号： G11C13/0064 ,  G11C13/0004 ,  G11C13/004 ,  G11C13/0069 ,  G11C29/028 ,  G11C29/50 ,  G11C29/50008 ,  G11C2013/0054 ,  G11C2213/72

    摘要： To realize a fast and highly reliable phase-change memory system of low power consumption, a semiconductor device includes: a memory device which includes a first memory array having a first area including a plurality of first memory cells and a second area including a plurality of second memory cells; a controller coupled to the memory device to issue a command to the memory device; and a condition table for storing a plurality of trial writing conditions. The controller performs trial writing in the plurality of second memory cells a plurality of times based on the plurality of trial writing conditions stored in the condition table, and determines writing conditions in the plurality of first memory cells based on a result of the trial writing. The memory device performs writing in the plurality of first memory cells based on the writing conditions instructed from the controller.

    摘要翻译： 为了实现低功耗的快速且高度可靠的相变存储器系统，半导体器件包括：存储器件，其包括具有包括多个第一存储器单元的第一区域的第一存储器阵列和包括多个第一存储器单元的第二区域 第二存储单元; 控制器，其耦合到所述存储器设备以向所述存储器设备发出命令; 以及用于存储多个试写条件的条件表。 控制器基于存储在条件表中的多个试写条件，在多个第二存储单元中执行多次尝试写入，并且基于试写的结果来确定多个第一存储单元中的写入条件。 存储器件基于从控制器指示的写入条件在多个第一存储器单元中执行写入。

    Semiconductor device
    32.
    发明授权
    Semiconductor device 失效
    半导体器件

    公开(公告)号：US07885102B2

    公开(公告)日：2011-02-08

    申请号：US12377271

    申请日：2006-09-15

    申请人： Satoru Hanzawa ,  Yoshikazu Iida

    发明人： Satoru Hanzawa ,  Yoshikazu Iida

    IPC分类号： G11C11/00

    CPC分类号： G11C13/0069 ,  G11C13/0004 ,  G11C13/004 ,  G11C2213/79

    摘要： In a memory array MCA which includes memory cells MC each having a variable-resistance-based memory device RQ and a select transistor MQ, an object is to receive a fixed quantity of storage data for a short time, and to realize writing operation to the memory cell, with suppressed peak current. In order to achieve the object, the data bus occupation time in rewriting operation is shortened by using plural sense amplifiers and storing storage data temporarily, and plural programming circuits are provided and activated using the control signals with different phases. By the above, the phase change memory system with low current consumption can be realized, without causing degradation of the utilization ratio of the data bus.

    摘要翻译： 在包括具有可变电阻的存储器件RQ和选择晶体管MQ的存储单元MC的存储器阵列MCA中，目的是在短时间内接收固定量的存储数据，并且实现对 存储单元，具有抑制的峰值电流。 为了实现该目的，通过使用多个读出放大器和临时存储存储数据来缩短重写操作中的数据总线占用时间，并且使用具有不同相位的控制信号来提供和激活多个编程电路。 通过上述，可以实现具有低电流消耗的相变存储器系统，而不会降低数据总线的利用率。

    Semiconductor device
    34.
    发明授权
    Semiconductor device 失效
    半导体器件

    公开(公告)号：US06862232B2

    公开(公告)日：2005-03-01

    申请号：US10726658

    申请日：2003-12-04

    申请人： Satoru Hanzawa ,  Takeshi Sakata

    发明人： Satoru Hanzawa ,  Takeshi Sakata

    IPC分类号： G11C11/15 ,  G11C5/00 ,  G11C7/00 ,  G11C11/00 ,  G11C11/16 ,  G11C11/34 ,  H01L27/22 ,  H01L31/0328

    CPC分类号： G11C29/787 ,  G11C7/14 ,  G11C11/1673 ,  G11C11/1693

    摘要： A dummy cell includes a plurality of first memory cells MC for storing “1” or “0”, arranged at points of intersection between a plurality of word lines WR0 to WR7 and a plurality of first data lines D0 to D7, a plurality of first dummy cells MCH for storing “1” or “0”, arranged at points of intersection between the word lines WR0 to WR7 and a first dummy data line, and a plurality of second dummy cells MCL for storing “0”, arranged at points of intersection between the word lines WR0 to WR7 and a second dummy data line DD1.

    摘要翻译： 虚拟单元包括多个用于存储“1”或“0”的第一存储单元MC，其布置在多个字线WR0至WR7与多个第一数据线D0至D7之间的交点处，多个第一 用于存储“1”或“0”的虚拟单元MCH，布置在字线WR0至WR7和第一虚拟数据线之间的交点处，以及多个第二虚拟单元MCL，用于存储“0” 字线WR0〜WR7与第二伪数据线DD1的交点。

    Semiconductor memory device equipped with dummy cells
    36.
    发明授权
    Semiconductor memory device equipped with dummy cells 失效
    装有虚拟电池的半导体存储器件

    公开(公告)号：US06512714B2

    公开(公告)日：2003-01-28

    申请号：US09942558

    申请日：2001-08-31

    申请人： Satoru Hanzawa ,  Takeshi Sakata

    发明人： Satoru Hanzawa ,  Takeshi Sakata

    IPC分类号： G11C702

    CPC分类号： G11C11/4099 ,  G11C7/14

    摘要： There are provided a reference voltage generating method used for reading out operation of a memory cell having amplification ability, and a dummy cell. The memory cell is composed of a read NMOS transistor, a write transistor, and a coupled-capacitance. The dummy cell is made such that two memory cells are connected in series. The dummy cell is arranged at the most far end of each of the data lines against the sense amplifier. A reference voltage is generated by making a difference in an amount of current flowing in each of the read NMOS transistors of the memory cell and the dummy cell. As a result, DRAM showing a higher speed, a higher integration and a lower electrical power as compared with those of the prior art device can be realized.

    摘要翻译： 提供了用于读出具有放大能力的存储单元的操作的参考电压产生方法和虚拟单元。 存储单元由读取NMOS晶体管，写入晶体管和耦合电容构成。 虚拟单元被制成使得两个存储单元串联连接。 每个数据线的最远端布置在相对于读出放大器的虚拟单元。 通过使存储单元的读取NMOS晶体管和虚设单元中的每一个中流动的电流量的差异来产生参考电压。 结果，可以实现与现有技术的装置相比显示更高速度，更高集成度和更低电力的DRAM。

    Semiconductor integrated circuit having a clock recovery circuit
    37.
    发明授权
    Semiconductor integrated circuit having a clock recovery circuit 有权
    具有时钟恢复电路的半导体集成电路

    公开(公告)号：US06281725B1

    公开(公告)日：2001-08-28

    申请号：US09337421

    申请日：1999-06-22

    申请人： Satoru Hanzawa ,  Takeshi Sakata ,  Katsutaka Kimura

    发明人： Satoru Hanzawa ,  Takeshi Sakata ,  Katsutaka Kimura

    IPC分类号： H03L700

    CPC分类号： H03K5/135 ,  H03K5/133 ,  H03L7/0814 ,  H03L7/0818 ,  H04L7/0008

    摘要： A clock recovery circuit is provided for use in a memory with a clock synchronized interface or the like, wherein an external clock is temporarily intercepted to shorten the lock-in time when an internal clock is to be generated from the external clock. The clock recovery circuit includes a delay circuit array, into which an external clock is inputted, for generating a plurality of reference clocks, a control circuit for comparing the phases of the external clock and of the plurality of reference clocks and detecting the number of delay stages of the delay circuits required for locking in, and latching circuit for holding the number of delay stages required for locking in. Once synchronism is detected and the number of delay stages required for locking in are held in the latching circuit, the generation of the internal clock can be resumed in a short period of time even if the supply of the external clock is temporarily suspended.

    摘要翻译： 提供了一种用于具有时钟同步接口等的存储器中的时钟恢复电路，其中暂时截取外部时钟以缩短当从外部时钟产生内部时钟时的锁定时间。时钟恢复 电路包括：输入外部时钟的延迟电路阵列，用于产生多个参考时钟;控制电路，用于比较外部时钟和多个参考时钟的相位，并且检测所述多个参考时钟的延迟级数 锁定所需的延迟电路和用于保持锁定所需的延迟级数的锁存电路。一旦检测到同步，锁定所需的延迟级数被保持在锁存电路中，则产生内部时钟可以 即使暂时停止外部时钟的供给，也可以在短时间内恢复。

    Phase control circuit, semiconductor device and semiconductor memory
    38.
    发明授权
    Phase control circuit, semiconductor device and semiconductor memory 有权

    公开(公告)号：US06222792B1

    公开(公告)日：2001-04-24

    申请号：US09666598

    申请日：2000-09-20

    申请人： Satoru Hanzawa ,  Takeshi Sakata ,  Osamu Nagashima

    发明人： Satoru Hanzawa ,  Takeshi Sakata ,  Osamu Nagashima

    IPC分类号： G11C800

    CPC分类号： G11C7/1057 ,  G11C7/1051 ,  G11C7/22 ,  G11C7/222

    摘要： A phase control circuit comprises a plurality of fixed delay circuits (200-0 through 200-5) which assign different predetermined delay times to a first clock signal (BDA1) respectively, a detection circuit (201) which receives clock signals outputted from the plurality of fixed delay circuits and a second clock signal (PCLK) different in phase from the first clock signal therein and generates detected signals (202) represented in a plurality of bits each corresponding to the difference in phase between the first clock signal and the second clock signal, and a variable delay circuit (200-6) which gives a delay in the phase difference corresponding to each of the detected signals to a third clock signal (BDA2).

    Semiconductor storage apparatus or semiconductor memory module
    40.
    发明授权
    Semiconductor storage apparatus or semiconductor memory module 有权
    半导体存储装置或半导体存储器模块

    公开(公告)号：US08614922B2

    公开(公告)日：2013-12-24

    申请号：US13327585

    申请日：2011-12-15

    申请人： Satoru Hanzawa

    发明人： Satoru Hanzawa

    IPC分类号： G11C7/00

    CPC分类号： G11C7/22 ,  G11C7/1039 ,  G11C7/1042 ,  G11C13/0004 ,  G11C13/0007 ,  G11C13/004 ,  G11C13/0061 ,  G11C13/0064 ,  G11C13/0069 ,  G11C2207/2209 ,  G11C2207/2245 ,  G11C2211/5623 ,  G11C2211/5624

    摘要： A semiconductor storage apparatus provides a large capacity phase-change memory possessing high speed operation, low electrical current, and high-reliability. During the period that a read-out start signal is activated in the memory region control circuit, and the block of pairs of sense-latch and write driver is performing the verify read in the upper section memory region, the write enable signals in the memory region control circuit are activated and the block of pairs of sense-latch and write driver performs rewrite operation of the data in the lower section memory region. This type of operation allows cancelling out the time required for the verify read and the time required for the time-division write operation by performing the verify read in one memory region, while performing time-division rewrite in other memory region, to achieve both higher reliability rewrite operation along with suppressing the rewrite operation peak electrical current.

    摘要翻译： 半导体存储装置提供具有高速运行，低电流和高可靠性的大容量相变存储器。 在存储器区域控制电路中激活读出开始信号的期间，并且读出驱动器对的块对在上部存储区进行验证读取，存储器中的写使能信号 区域控制电路被激活，并且一对感测锁存器和写入驱动器执行下部存储器区域中的数据的重写操作。 这种类型的操作允许通过在一个存储器区域中执行验证读取同时在其他存储器区域中执行时分重写来消除验证读取所需的时间和时分写入操作所需的时间，以实现更高的 可靠性重写操作以及抑制重写操作峰值电流。