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    Manufacturing Method of Non-Planar FET
    31.
    发明申请
    Manufacturing Method of Non-Planar FET 有权
    非平面FET的制造方法

    公开(公告)号：US20150004766A1

    公开(公告)日：2015-01-01

    申请号：US14487103

    申请日：2014-09-16

    Applicant: UNITED MICROELECTRONICS CORP.

    Inventor： Shih-Hung Tsai ,  Ssu-I Fu ,  Ying-Tsung Chen ,  Chih-Wei Chen ,  Ying-Chih Lin ,  Chien-Ting Lin ,  Hsuan-Hsu Chen

    IPC: H01L29/66 ,  H01L29/51

    CPC classification number: H01L29/66795 ,  H01L29/51 ,  H01L29/66818 ,  H01L29/785

    Abstract: The present invention provides a non-planar FET which includes a substrate, a fin structure, a sub spacer, a gate, a dielectric layer and a source/drain region. The fin structure is disposed on the substrate. The sub spacer is disposed only on a middle sidewall of the fin structure. The gate is disposed on the fin structure. The dielectric layer is disposed between the fin structure and the gate. The source/drain region is disposed in the fin structure. The present invention further provides a method of forming the same.

    Abstract translation: 本发明提供一种非平面FET，其包括基板，鳍结构，子间隔物，栅极，电介质层和源极/漏极区域。 翅片结构设置在基板上。 子间隔件仅设置在翅片结构的中间侧壁上。 门设置在翅片结构上。 介电层设置在翅片结构和栅极之间。 源/漏区设置在鳍结构中。 本发明还提供一种形成该方法的方法。

    METHOD FOR MANUFACTURING SEMICONDUCTOR DEVICES
    32.
    发明申请
    METHOD FOR MANUFACTURING SEMICONDUCTOR DEVICES 有权
    制造半导体器件的方法

    公开(公告)号：US20140349452A1

    公开(公告)日：2014-11-27

    申请号：US13899581

    申请日：2013-05-22

    Applicant: UNITED MICROELECTRONICS CORP.

    Inventor： Jun-Jie Wang ,  Po-Chao Tsao ,  Chia-Jui Liang ,  Shih-Fang Tzou ,  Chien-Ting Lin

    IPC: H01L21/8234

    CPC classification number: H01L21/823468 ,  H01L21/82345 ,  H01L21/823462 ,  H01L21/823842 ,  H01L21/823857 ,  H01L21/823864 ,  H01L27/0629 ,  H01L29/66545 ,  H01L29/7843 ,  H01L29/7848 ,  H01L29/785

    Abstract: A method for manufacturing a semiconductor device is provided. A first stack structure and a second stack structure are formed to respectively cover a portion of a first fin structure and a second fin structure. Subsequently, a spacer is respectively formed on the sidewalls of the fin structures through an atomic layer deposition process and the composition of the spacers includes silicon carbon nitride. Afterwards, a interlayer dielectric is formed and etched so as to expose the hard mask layers. A mask layer is formed to cover the second stack structure and a portion of the dielectric layer. Later, the hard mask layer in the first stack structure is removed under the coverage of the mask layer. Then, a dummy layer in the first stack structure is replaced with a conductive layer.

    Abstract translation: 提供一种制造半导体器件的方法。 形成第一堆叠结构和第二堆叠结构以分别覆盖第一鳍结构和第二鳍结构的一部分。 随后，通过原子层沉积工艺分别在翅片结构的侧壁上形成间隔物，间隔物的组成包括硅氮化硅。 之后，形成并蚀刻层间电介质，以露出硬掩模层。 形成掩模层以覆盖第二堆叠结构和介电层的一部分。 之后，在掩模层的覆盖下去除第一堆叠结构中的硬掩模层。 然后，第一堆叠结构中的虚设层被导电层代替。

    MANUFACTURING METHOD FOR SEMICONDUCTOR DEVICE HAVING METAL GATE
    34.
    发明申请
    MANUFACTURING METHOD FOR SEMICONDUCTOR DEVICE HAVING METAL GATE 有权
    具有金属栅的半导体器件的制造方法

    公开(公告)号：US20140106557A1

    公开(公告)日：2014-04-17

    申请号：US14140546

    申请日：2013-12-26

    Applicant: UNITED MICROELECTRONICS CORP.

    Inventor： Ssu-I Fu ,  Wen-Tai Chiang ,  Ying-Tsung Chen ,  Shih-Hung Tsai ,  Chien-Ting Lin ,  Chi-Mao Hsu ,  Chin-Fu Lin

    IPC: H01L21/28 ,  H01L21/8238

    CPC classification number: H01L21/28114 ,  H01L21/28088 ,  H01L21/823828 ,  H01L21/823842 ,  H01L29/4966 ,  H01L29/517 ,  H01L29/66545 ,  H01L29/6659 ,  H01L29/7833

    Abstract: A manufacturing method for semiconductor device having metal gate includes providing a substrate having a first semiconductor device and a second semiconductor device formed thereon, the first semiconductor device having a first gate trench and the second semiconductor device having a second gate trench; sequentially forming a high dielectric constant (high-k) gate dielectric layer and a multiple metal layer on the substrate; forming a first work function metal layer in the first gate trench; performing a first pull back step to remove a portion of the first work function metal layer from the first gate trench; forming a second work function metal layer in the first gate trench and the second gate trench; and performing a second pull back step to remove a portion of the second work function metal layer from the first gate trench and the second gate trench.

    Abstract translation: 具有金属栅极的半导体器件的制造方法包括提供具有第一半导体器件和形成在其上的第二半导体器件的衬底，所述第一半导体器件具有第一栅极沟槽，所述第二半导体器件具有第二栅极沟槽; 在基板上依次形成高介电常数（高k）栅介质层和多金属层; 在所述第一栅极沟槽中形成第一功函数金属层; 执行第一拉回步骤以从所述第一栅极沟槽去除所述第一功函数金属层的一部分; 在所述第一栅极沟槽和所述第二栅极沟槽中形成第二功函数金属层; 以及执行第二拉回步骤以从所述第一栅极沟槽和所述第二栅极沟槽去除所述第二功函数金属层的一部分。

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