公开(公告)号：US20140091383A1

公开(公告)日：2014-04-03

申请号：US14098290

申请日：2013-12-05

Applicant: United Microelectronics Corp.

Inventor： Ko-Chi Chen ,  Ping-Chia Shih ,  Chih-Ming Wang ,  Chi-Cheng Huang ,  Hsiang-Chen Lee

IPC: H01L29/792 ,  H01L29/78

CPC classification number: H01L29/792 ,  H01L27/11573 ,  H01L29/40117 ,  H01L29/665 ,  H01L29/66833 ,  H01L29/7833

Abstract: A method for fabricating a semiconductor device is described. A stacked gate dielectric is formed over a substrate, including a first dielectric layer, a second dielectric layer and a third dielectric layer from bottom to top. A conductive layer is formed on the stacked gate dielectric and then patterned to form a gate conductor. The exposed portion of the third and the second dielectric layers are removed with a selective wet cleaning step. S/D extension regions are formed in the substrate with the gate conductor as a mask. A first spacer is formed on the sidewall of the gate conductor and a portion of the first dielectric layer exposed by the first spacer is removed. S/D regions are formed in the substrate at both sides of the first spacer. A metal silicide layer is formed on the S/D regions.

Abstract translation: 对半导体装置的制造方法进行说明。 堆叠的栅极电介质形成在衬底上，包括从底部到顶部的第一介电层，第二电介质层和第三电介质层。 在堆叠的栅极电介质上形成导电层，然后将其图案化以形成栅极导体。 通过选择性湿式清洗步骤除去第三和第二介电层的暴露部分。 在栅极导体作为掩模的基板中形成S / D延伸区域。 在栅极导体的侧壁上形成第一间隔物，并且去除由第一间隔物露出的第一电介质层的一部分。 在第一间隔物的两侧的基板中形成S / D区域。 在S / D区域上形成金属硅化物层。

公开(公告)号：US20240304657A1

公开(公告)日：2024-09-12

申请号：US18128218

申请日：2023-03-29

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Yi-Chun Teng ,  Ming-Che Tsai ,  Ping-Chia Shih ,  Yi-Chang Huang ,  Wen-Lin Wang ,  Yu-Fan Hu ,  Ssu-Yin Liu ,  Yu-Nong Chen ,  Pei-Tsen Shiu ,  Cheng-Tzung Tsai

IPC: H01L27/06

CPC classification number: H01L28/24 ,  H01L27/0629

Abstract: A semiconductor device includes a substrate, a first gate, a plurality of second gates and a resistor. The substrate is defined with an active region and a resistor region. The first gate is disposed in the active region. The first gate has a first length extending along a first direction and a second length extending along a second direction. The plurality of second gates are disposed in the resistor region. Each of the second gates has a third length extending along the first direction and a fourth length extending along the second direction. The first length is equal to the third length, and the second length is equal to the fourth length. The resistor is disposed on the plurality of second gates.

公开(公告)号：US20190378846A1

公开(公告)日：2019-12-12

申请号：US16005422

申请日：2018-06-11

Applicant: United Microelectronics Corp.

Inventor： Zi-Jun Liu ,  Ping-Chia Shih ,  Chi-Cheng Huang ,  Kuo-Lung Li ,  Hung-Wei Lin ,  An-Hsiu Cheng ,  Chih-Hao Pan ,  Cheng-Hua Chou ,  Chih-Hung Wang

IPC: H01L27/112 ,  H01L27/11521 ,  H01L27/1156 ,  H01L21/762

Abstract: Provided is a semiconductor structure including a substrate, an isolation structure, a fuse and two gate electrodes. The isolation structure is located in the substrate and defines active regions of the substrate. The fuse is disposed on the isolation structure. The gate electrodes are disposed on the active regions and connected to ends of the fuse. In an embodiment, a portion of a bottom surface of the fuse is lower than top surfaces of the active regions of the substrate.

公开(公告)号：US20190043877A1

公开(公告)日：2019-02-07

申请号：US15665437

申请日：2017-08-01

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Kuo-Lung Li ,  Ping-Chia Shih ,  Wen-Peng Hsu ,  Chia-Wen Wang ,  Meng-Chun Chen ,  Chih-Hao Pan

IPC: H01L27/11568 ,  H01L29/423

Abstract: A non-volatile memory device includes a semiconductor substrate, a control gate electrode, a first oxide-nitride-oxide (ONO) structure, a selecting gate electrode, a second ONO structure, and a spacer structure. The control gate electrode and the selecting gate electrode are disposed on the semiconductor substrate. The first ONO structure is disposed between the control gate electrode and the semiconductor substrate. The second ONO structure is disposed between the control gate electrode and the selecting gate electrode in a first direction. The spacer structure is disposed between the control gate electrode and the second ONO structure in the first direction. A distance between the control gate electrode and the selecting gate electrode in the first direction is smaller than or equal to a sum of a width of the second ONO structure and a width of the spacer structure in the first direction.

公开(公告)号：US20180211966A1

公开(公告)日：2018-07-26

申请号：US15927914

申请日：2018-03-21

Applicant: United Microelectronics Corp.

Inventor： Chia-Wen Wang ,  Hsiang-Chen Lee ,  Wen-Peng Hsu ,  Kuo-Lung Li ,  Meng-Chun Chen ,  Zi-Jun Liu ,  Ping-Chia Shih

IPC: H01L27/1157 ,  H01L21/28 ,  H01L29/66 ,  H01L27/11573 ,  H01L27/11543 ,  H01L29/792 ,  H01L27/11563 ,  H01L29/78

CPC classification number: H01L27/1157 ,  H01L27/11543 ,  H01L27/11563 ,  H01L27/11573 ,  H01L29/40114 ,  H01L29/40117 ,  H01L29/6656 ,  H01L29/6659 ,  H01L29/66833 ,  H01L29/7833 ,  H01L29/7881 ,  H01L29/792

Abstract: A method for fabricating a semiconductor structure is shown. A first gate of a first device and a second gate of a second device are formed over a semiconductor substrate. First LDD regions are formed in the substrate beside the first gate using the first gate as a mask. A conformal layer is formed covering the first gate, the second gate and the substrate, wherein the conformal layer has sidewall portions on sidewalls of the second gate. Second LDD regions are formed in the substrate beside the second gate using the second gate and the sidewall portions of the conformal layer as a mask.

公开(公告)号：US09331183B2

公开(公告)日：2016-05-03

申请号：US13909057

申请日：2013-06-03

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Hsiang-Chen Lee ,  Ping-Chia Shih ,  Chi-Cheng Huang ,  Wan-Fang Chung ,  Yu-Chun Chang ,  Je-Yi Su

IPC: H01L29/792 ,  H01L29/66 ,  H01L21/28 ,  H01L29/423 ,  H01L27/115

CPC classification number: H01L29/66833 ,  H01L21/02164 ,  H01L21/02167 ,  H01L21/0217 ,  H01L21/02271 ,  H01L21/0332 ,  H01L21/28282 ,  H01L27/11568 ,  H01L29/42348 ,  H01L29/792 ,  H01L29/7923

Abstract: A semiconductor device including a first gate structure and a second gate structure immediately adjacent to each other with a spacer therebetween. Line width of the top of the second gate structure is not less than that of the bottom thereof. A fabrication method thereof is also disclosed. A transient first gate structure and a temporary gate structure are formed by etching through a first hard mask. A second gate structure is formed between a first spacer and a second spacer opposite to each other and disposed respectively on the transient first gate structure and temporary gate structure. The second gate structure is covered with a second hard mask. An etch process is performed through a patterned photoresist layer to remove exposed first hard mask and temporary gate structure and to partially remove exposed portion of first hard mask and transient first gate structure to form the first gate structure.

Abstract translation: 一种半导体器件，包括彼此紧邻的第一栅极结构和第二栅极结构，其间具有间隔物。 第二栅极结构的顶部的线宽不小于其底部的线宽。 还公开了其制造方法。 通过蚀刻穿过第一硬掩模形成瞬态第一栅极结构和临时栅极结构。 第二栅极结构形成在第一间隔物和彼此相对的第二间隔物之间​​，分别设置在瞬态第一栅极结构和临时栅极结构上。 第二个门结构用第二个硬掩模覆盖。 通过图案化的光致抗蚀剂层进行蚀刻处理以去除暴露的第一硬掩模和临时栅极结构，并且部分地去除第一硬掩模和瞬态第一栅极结构的暴露部分以形成第一栅极结构。

公开(公告)号：US09040423B2

公开(公告)日：2015-05-26

申请号：US13943900

申请日：2013-07-17

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Wan-Fang Chung ,  Ping-Chia Shih ,  Hsiang-Chen Lee ,  Che-Hao Chang ,  Jhih-Long Lin ,  Wei-Pin Huang ,  Shao-Nung Huang ,  Yu-Cheng Wang ,  Jaw-Jiun Tu ,  Chung-Che Huang

IPC: H01L21/311 ,  H01L21/306

CPC classification number: H01L21/306 ,  H01L21/30604 ,  H01L21/31105 ,  H01L21/32139 ,  H01L27/11534 ,  H01L29/66825

Abstract: A method for manufacturing a semiconductor device is provided. A substrate having a first area with a first poly layer and a second area with a second poly layer is provided. A nitride HM film is then deposited above the first poly layer of a first device in the first area and above the second poly layer in the second area. Afterwards, a first patterned passivation is formed on the nitride HM film in the first area to cover the nitride HM film and the first device, and a second patterned passivation is formed above the second poly layer in the second area. The second poly layer in the second area is defined by the second patterned passivation.

Abstract translation: 提供一种制造半导体器件的方法。 提供了具有第一区域和第二多晶硅层的基板，第一区域具有第一多晶硅层和第二区域。 然后在第二区域中的第一区域中的第一多晶硅层的第一多晶硅层之上沉积氮化物HM膜，并在第二区域中的第二多晶硅层上方沉积氮化物HM膜。 之后，在第一区域中的氮化物HM膜上形成第一图案化钝化物以覆盖氮化物HM膜和第一器件，并且在第二区域中的第二多晶硅层之上形成第二图案化钝化。 第二区域中的第二多晶硅层由第二图案化钝化限定。