公开(公告)号：US06745279B2

公开(公告)日：2004-06-01

申请号：US09962257

申请日：2001-09-26

申请人： Yuichiro Morita ,  Manabu Jyou ,  Yasuhiro Nakatsuka ,  Tetsuya Shimomura ,  Yutaka Okada ,  Kazushige Yamagishi

发明人： Yuichiro Morita ,  Manabu Jyou ,  Yasuhiro Nakatsuka ,  Tetsuya Shimomura ,  Yutaka Okada ,  Kazushige Yamagishi

IPC分类号： G06F1200

CPC分类号： G06F13/161

摘要： A memory controller is disclosed, in which upon receipt of an access request from a device, the memory controller activates a page designated by a row address of a first bank at a predetermined memory cycle, based on the access request. After that, before the read access to a page of the first bank, a second bank next to be accessed is precharged. In the case where a page mishit occurs due to the access from the first bank to the second bank by the graphic processing after the access to the first bank by the read operation, the memory controller activates the second bank immediately without precharging.

摘要翻译： 公开了一种存储器控制器，其中在从设备接收到访问请求时，存储器控制器基于访问请求以预定的存储器周期来激活由第一存储体的行地址指定的页面。 之后，在对第一个银行的页面的读取访问之前，接下来要访问的第二个银行被预充电。 在通过读取操作访问第一存储体之后，由于通过图形处理从第一存储体到第二存储体的访问发生页面错误的情况下，存储器控制器立即激活第二存储体而不进行预充电。

公开(公告)号：US06587111B2

公开(公告)日：2003-07-01

申请号：US09983716

申请日：2001-10-25

申请人： Atsushi Nakamura ,  Yasuhiro Nakatsuka ,  Kazushige Yamagishi

发明人： Atsushi Nakamura ,  Yasuhiro Nakatsuka ,  Kazushige Yamagishi

IPC分类号： G06T100

CPC分类号： G06T15/005 ,  G09G5/363 ,  G09G5/393 ,  G09G5/399 ,  G09G2340/10 ,  H04N7/0132

摘要： A graphic processor including a rendering control circuit which carries out weighted averaging on pieces of pixel data of source image information arranged to form a pixel-data matrix corresponding to a pixel matrix with columns of the pixel-data matrix being oriented perpendicularly to a scanning direction in order to compute a weighted average of pieces of pixel data on rows of the pixel-data matrix adjacent to each other and on a column of the pixel-data matrix perpendicular to the scanning direction in so-called blend processing. The rendering control circuit reads out pieces of pixel data from the pixel-data matrix sequentially in a direction perpendicular to the scanning direction and computes a weighted average of the pieces of data. Image data subjected to blend processing is displayed by adopting an interlace scanning technique thereby eliminating undesired flicker.

公开(公告)号：US5968160A

公开(公告)日：1999-10-19

申请号：US923632

申请日：1997-09-04

申请人： Masahiko Saito ,  Kenichi Kurosawa ,  Yoshiki Kobayashi ,  Tadaaki Bandoh ,  Masahiro Iwamura ,  Takashi Hotta ,  Yasuhiro Nakatsuka ,  Shigeya Tanaka ,  Takeshi Takemoto

发明人： Masahiko Saito ,  Kenichi Kurosawa ,  Yoshiki Kobayashi ,  Tadaaki Bandoh ,  Masahiro Iwamura ,  Takashi Hotta ,  Yasuhiro Nakatsuka ,  Shigeya Tanaka ,  Takeshi Takemoto

IPC分类号： G06F9/30 ,  G06F9/318 ,  G06F9/38 ,  G06F12/08 ,  G06F15/173 ,  G06F15/80 ,  G06F15/16

CPC分类号： G06F9/3891 ,  G06F12/084 ,  G06F15/17381 ,  G06F15/8015 ,  G06F9/30087 ,  G06F9/3009 ,  G06F9/30181 ,  G06F9/3802 ,  G06F9/3814 ,  G06F9/3822 ,  G06F9/3824 ,  G06F9/3836 ,  G06F9/3851 ,  G06F9/3885

摘要： A data processing system having flexibility coping with parallelism of a program comprises a plurality of processor elements for executing instructions, a main memory shared by the plurality of processor elements, and a plurality of parallel operation control facilities for enabling the plurality of processor elements to operate in synchronism. The plurality of parallel operation control facilities are provided in correspondence to the plurality of processor elements, respectively. The data processing system further comprises a multiprocessor operation control facility for enabling the plurality of processor elements to operate independently, and a flag for holding a value indicating which of the parallel operation mode or the multiprocessor mode is to be activated. The shared cache memory is implemented in a blank instruction and controlled by a cache controller so that inconsistency of the data stored in the cache memory is eliminated.

摘要翻译： 具有应对程序的并行性的灵活性的数据处理系统包括用于执行指令的多个处理器元件，由多个处理器元件共享的主存储器和用于使多个处理器元件能够操作的多个并行操作控制设备 同步。 分别对应于多个处理器元件提供多个并行操作控制设备。 数据处理系统还包括多处理器操作控制设备，用于使多个处理器元件能够独立地操作，以及用于保持指示并行操作模式或多处理器模式中的哪一个被激活的值的标志。 共享高速缓冲存储器以空白指令实现并由高速缓存控制器控制，从而消除了存储在高速缓冲存储器中的数据的不一致性。

公开(公告)号：US5506982A

公开(公告)日：1996-04-09

申请号：US278245

申请日：1994-07-21

申请人： Takashi Hotta ,  Kozaburo Kurita ,  Masahiro Iwamura ,  Hideo Maejima ,  Shigeya Tanaka ,  Tadaaki Bandoh ,  Yasuhiro Nakatsuka ,  Kazuo Kato ,  Sin-ichi Sinoda

发明人： Takashi Hotta ,  Kozaburo Kurita ,  Masahiro Iwamura ,  Hideo Maejima ,  Shigeya Tanaka ,  Tadaaki Bandoh ,  Yasuhiro Nakatsuka ,  Kazuo Kato ,  Sin-ichi Sinoda

IPC分类号： G06F1/10 ,  H03K5/156 ,  H03L7/18 ,  G06F1/06

CPC分类号： H03K5/1565 ,  G06F1/10 ,  H03L7/18

摘要： An information processing system having an original clock oscillator for delivering at least one original clock signal K defined as a first clock signal and a plurality of information processing units supplied with the original clock signal K, wherein each information processing unit comprises clock generating means for generating at least one second clock signal K.sub.1 which is phase-locked with the original clock signal K and which has a predetermined duty cycle and a logic device whose operation timing is controlled by the second clock signal K.sub.1, and the operation timing of an interface provided between at least one pair of logic devices is synchronously controlled by the clock signal K.sub.1.

公开(公告)号：US07814223B2

公开(公告)日：2010-10-12

申请号：US12010762

申请日：2008-01-29

申请人： Hiroshi Arita ,  Yasuhiro Nakatsuka ,  Yasuwo Watanabe ,  Kei Ouchi ,  Yoshihiro Tanaka ,  Toshinobu Kanai ,  Masanobu Tanaka ,  Kenji Furuhashi ,  Tomoaki Aoki

发明人： Hiroshi Arita ,  Yasuhiro Nakatsuka ,  Yasuwo Watanabe ,  Kei Ouchi ,  Yoshihiro Tanaka ,  Toshinobu Kanai ,  Masanobu Tanaka ,  Kenji Furuhashi ,  Tomoaki Aoki

IPC分类号： G06F13/00

CPC分类号： H04L47/6255 ,  H04L12/44 ,  H04L47/10 ,  H04L47/2458 ,  H04L47/30 ,  H04L47/522 ,  H04L49/205 ,  H04L49/3018 ,  H04L49/351

摘要： A transmit packet generated by a CPU 1 is held in a buffer 100a (100b). From among packets received from Ethernet 820a (820b), a packet, a destination of which is a communication device 800, is held in the buffer 100a (100b). A packet which should be transmitted is transmitted from a transfer judging circuit 200 to Ethernet 820a or 820b through a MAC unit 300a or 300b. If a transfer judging circuit 200 judges a packet from the Ethernet 820a to be a packet, a destination of which is another communication device, with reference to a destination MAC address, this packet is transferred to the Ethernet 820b through MAC 300b. If a usage rate of a transferring FIFO buffer 130a (130b) exceeds a threshold value in the process of transmitting a packet held in a transmitting FIFO buffer 120a (130b) on a priority basis, the priority order of a transfer packet is made higher than that of a transmit packet so that the transfer packet is transferred to the Ethernet 820a or 820b in preference to the transmit packet. This prevents a transfer buffer means from overflowing.

摘要翻译： 由CPU1生成的发送包被保存在缓冲器100a（100b）中。 从从以太网820a（820b）接收的分组中，其目的地是通信设备800的分组被保存在缓冲器100a（100b）中。 应该发送的分组通过MAC单元300a或300b从传送判断电路200发送到以太网820a或820b。 如果传输判断电路200将来自以太网820a的分组判断为分组，则其目的地是另一个通信设备，参考目的地MAC地址，该分组通过MAC 300b被传送到以太网820b。 如果传送FIFO缓冲器130a（130b）的使用率在发送FIFO缓冲器120a（130b）中保持的分组的优先级的基础上超过阈值，则传送分组的优先级顺序高于 传输分组的传输分组优先于传送分组传送到以太网820a或820b。 这防止了传送缓冲器装置溢出。

公开(公告)号：US20100030421A1

公开(公告)日：2010-02-04

申请号：US12575212

申请日：2009-10-07

申请人： Kentaro YOSHIMURA ,  Kohei Sakurai ,  Nobuyasu Kanekawa ,  Yuichiro Morita ,  Yoshiaki Takahashi ,  Kenichi Kurosawa ,  Toshimichi Minowa ,  Masatoshi Hoshino ,  Yasuhiro Nakatsuka ,  Kotaro Shimamura ,  Kunihiko Tsunedomi ,  Shoji Sasaki

发明人： Kentaro YOSHIMURA ,  Kohei Sakurai ,  Nobuyasu Kanekawa ,  Yuichiro Morita ,  Yoshiaki Takahashi ,  Kenichi Kurosawa ,  Toshimichi Minowa ,  Masatoshi Hoshino ,  Yasuhiro Nakatsuka ,  Kotaro Shimamura ,  Kunihiko Tsunedomi ,  Shoji Sasaki

IPC分类号： B60W10/00

CPC分类号： B60W30/00 ,  B60K6/46 ,  B60K6/52 ,  B60L3/0023 ,  B60L3/003 ,  B60L3/0076 ,  B60L3/0092 ,  B60L15/2009 ,  B60L2240/12 ,  B60L2240/20 ,  B60L2240/24 ,  B60L2240/423 ,  B60L2250/26 ,  B60T7/12 ,  B60W10/04 ,  B60W10/06 ,  B60W10/08 ,  B60W10/10 ,  B60W10/18 ,  B60W10/20 ,  B60W20/00 ,  B60W40/08 ,  B60W40/10 ,  B60W50/02 ,  B60W50/0225 ,  B60W50/04 ,  B60W2510/20 ,  B60W2510/202 ,  B60W2520/14 ,  B60W2540/10 ,  B60W2540/12 ,  B60W2550/20 ,  B62D5/046 ,  B62D5/0481 ,  B62D6/00 ,  G06F11/0796 ,  Y02T10/6217 ,  Y02T10/6265 ,  Y02T10/6286 ,  Y02T10/645 ,  Y02T10/72 ,  Y02T10/7275 ,  Y02T90/16

摘要： A vehicle control system which can ensure high reliability, real-time processing, and expandability with a simplified ECU configuration and a low cost by backing up an error through coordination in the entire system without increasing a degree of redundancy of individual controllers beyond the least necessary level. The vehicle control system comprises a sensor controller for taking in sensor signals indicating a status variable of a vehicle and an operation amount applied from a driver, a command controller for generating a control target value based on the sensor signals taken in by the sensor controller, and an actuator controller for receiving the control target value from the command controller and operating an actuator to control the vehicle, those three controller being interconnected via a network. The actuator controller includes a control target value generating unit for generating a control target value based on the sensor signals taken in by the sensor controller and received by the actuator controller via the network when the control target value generated by the command controller is abnormal, and controls the actuator in accordance with the control target value generated by the control target value generating unit.

摘要翻译： 一种车辆控制系统，可以通过简化的ECU配置和低成本确保高可靠性，实时处理和可扩展性，通过整个系统中的协调备份错误，而不会增加单个控制器的冗余程度，超出最不必要的范围 水平。 车辆控制系统包括：传感器控制器，用于接收指示车辆的状态变量的传感器信号和从驾驶员施加的操作量;命令控制器，用于基于由传感器控制器接收的传感器信号产生控制目标值; 以及致动器控制器，用于从命令控制器接收控制目标值并操作致动器来控制车辆，这三个控制器经由网络互连。 执行器控制器包括控制目标值产生单元，用于当由指令控制器产生的控制目标值异常时，基于由传感器控制器接收并由致动器控制器经由网络接收的传感器信号产生控制目标值;以及 根据由控制目标值产生单元产生的控制目标值来控制致动器。

公开(公告)号：US20070250184A1

公开(公告)日：2007-10-25

申请号：US11737850

申请日：2007-04-20

申请人： Hiroshi Arita ,  Yasuhiro Nakatsuka

发明人： Hiroshi Arita ,  Yasuhiro Nakatsuka

IPC分类号： G05B13/02

CPC分类号： G05B13/024 ,  G05B15/02 ,  G06Q10/04 ,  G06Q50/06

摘要： An optimizing control system includes at least a local control unit for controlling at least a control apparatus, an integration control apparatus for controlling a plurality of the local control units in integration fashion, and at least a control information standardization interface arranged between the local control unit and the integration control apparatus for standardizing the control information transmitted and received between the local control unit 31 and the integration control apparatus. The control information standardization interface includes a control condition information storage unit for storing the constraints, the evaluation function and the attribute information expressed by a predetermined standard physical quantity for controlling the local apparatus, and a physical quantity converter for converting the local physical status amount acquired from the local apparatus into a standard physical status amount and converting the optical setpoint calculated by the integration control apparatus into a local control goal value.

摘要翻译： 一种优化控制系统至少包括用于至少控制控制装置的本地控制单元，用于以集成方式控制多个本地控制单元的集成控制装置，以及布置在本地控制单元之间的控制信息标准化接口 以及用于使本地控制单元31和积分控制装置之间发送和接收的控制信息标准化的积分控制装置。 控制信息标准化接口包括：控制条件信息存储单元，用于存储用于控制本地设备的预定标准物理量表示的约束，评估功能和属性信息;以及物理量转换器，用于转换所获取的本地物理状态量 从本地装置进入标准物理状态量，并将由积分控制装置计算出的光学设定值转换为本地控制目标值。

公开(公告)号：US20050141683A1

公开(公告)日：2005-06-30

申请号：US11018355

申请日：2004-12-22

申请人： Yoshikazu Ishii ,  Setsuo Arita ,  Yuji Ichinose ,  Nao Saito ,  Daisuke Sinma ,  Yasuhiro Nakatsuka

发明人： Yoshikazu Ishii ,  Setsuo Arita ,  Yuji Ichinose ,  Nao Saito ,  Daisuke Sinma ,  Yasuhiro Nakatsuka

IPC分类号： H04N7/18 ,  H04J1/00 ,  H04L1/00 ,  H04L27/00 ,  H04M11/00

CPC分类号： H04L5/0094 ,  H04L5/0007 ,  H04L5/0037 ,  H04L5/0046 ,  H04L5/006

摘要： Using a network in which one master station modem 105 and multiple slave station modem 106, 107, 108 are physically connected by rudder connection or bus connection with a telecommunication line 121, the measurement result of the S/N ratio between the master station and slave stations is once collected in the master station at the initialization stage, pairs of the modulation method, by which all modems can demodulate at high probability, and transmission voltage are calculated based on this data, and the calculation is transmitted to all slave stations; and at a normal transmission stage, information regarding the coordination and control of the network is transmitted in accordance with this setting. Thus, one-to-multi communication is realized, guaranteeing an access right.

摘要翻译： 使用其中一个主站调制解调器105和多个从站调制解调器106,107,108通过与电信线路121的舵连接或总线连接物理连接的网络，主站和从站之间的S / N比的测量结果 在初始化阶段，主站一旦收集站，则可以根据该数据计算出所有调制解调器可以以高概率解调的调制方式对和传输电压，并将计算发送到所有从站; 并且在正常发送阶段，根据该设置发送关于网络的协调和控制的信息。 因此，实现一对多通信，保证访问权限。

公开(公告)号：US20050027921A1

公开(公告)日：2005-02-03

申请号：US10842638

申请日：2004-05-11

申请人： Teppei Hirotsu ,  Kotaro Shimamura ,  Noboru Sugihara ,  Yasuhiro Nakatsuka ,  Teruaki Sakata

发明人： Teppei Hirotsu ,  Kotaro Shimamura ,  Noboru Sugihara ,  Yasuhiro Nakatsuka ,  Teruaki Sakata

IPC分类号： G06F9/38 ,  G11C5/00

CPC分类号： G06F9/3814 ,  G06F9/3802

摘要： A prefetch address calculation unit detects a branch instruction and a data access instruction to be reliably executed from a series of instruction included in an entry that is stored in a buffer at 1 cycle and outputs a prefetch request of its target address to a control unit. Then, decoding types of the series of instruction that is included in the entry, and setting it at an instruction type flag, the prefetch address calculation unit masks the output of the instruction type flag that has been executed by using an address signal of the instruction that is being executing presently and outputs a location of the instruction for issuing a prefetch request. By a signal from a control unit, the prefetch address calculation unit clears an instruction type flag corresponding to the instruction that issued the prefetch request.

摘要翻译： 预取地址计算单元从包含在存储在缓冲器中的条目中的一系列指令以1个周期检测可靠地执行的分支指令和数据访问指令，并将其目标地址的预取请求输出到控制单元。 然后，对包含在条目中的一系列指令进行解码，并将其设置为指令类型标志，预取地址计算单元通过使用指令的地址信号来掩蔽已经执行的指令类型标志的输出 正在执行中，并且输出用于发出预取请求的指令的位置。 通过来自控制单元的信号，预取地址计算单元清除与发出预取请求的指令相对应的指令类型标志。

公开(公告)号：US06384831B1

公开(公告)日：2002-05-07

申请号：US09213172

申请日：1998-12-17

申请人： Atsushi Nakamura ,  Yasuhiro Nakatsuka ,  Kazushige Yamagishi

发明人： Atsushi Nakamura ,  Yasuhiro Nakatsuka ,  Kazushige Yamagishi

IPC分类号： G06F1516

CPC分类号： G06T15/005 ,  G09G5/363 ,  G09G5/393 ,  G09G5/399 ,  G09G2340/10 ,  H04N7/0132

摘要： In a graphic processor, a rendering control circuit carries out weighted averaging on pieces of pixel data of source image information arranged to form a pixel-data matrix corresponding to a pixel matrix with columns of the pixel-data matrix being oriented perpendicularly to a scanning direction in order to compute a weighted average of pieces of pixel data on rows of the pixel-data matrix adjacent to each other and on a column of the pixel-data matrix perpendicular to the scanning direction in so-called blend processing. It is thus possible to eliminate a difference in image information between adjacent scanning lines, which is big in some cases. In this case, the rendering control circuit reads out pieces of pixel data from the pixel-data matrix sequentially in a direction perpendicular to the scanning direction and computes a weighted average of the pieces of data. It is therefore unnecessary to newly install a storage means, such as a line buffer, in a display control circuit and, particularly, in the rendering control circuit. Thus, even when image data subjected to blend processing is displayed by adopting an interlace scanning technique, undesired flickering is not generated.

摘要翻译： 在图形处理器中，渲染控制电路对源图像信息的像素数据进行加权平均，该像素数据排列成与像素矩阵相对应的像素数据矩阵，像素数据矩阵的列垂直于扫描方向 以便在所谓的混合处理中计算与彼此相邻的像素数据矩阵的行上的像素数据的加权平均值以及垂直于扫描方向的像素数据矩阵的列。 因此，可以消除在某些情况下较大的相邻扫描线之间的图像信息的差异。 在这种情况下，渲染控制电路在与扫描方向垂直的方向上顺序地从像素数据矩阵中读出像素数据，并计算这些数据的加权平均值。 因此，不必在显示控制电路中，特别是在渲染控制电路中新安装诸如行缓冲器的存储装置。 因此，即使通过采用隔行扫描技术显示进行了混合处理的图像数据，也不会产生不期望的闪烁。