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46 条记录 (耗时 0.038 秒)

    Semiconductor device structure and methods of manufacturing the same
    31.
    发明授权
    Semiconductor device structure and methods of manufacturing the same 有权
    半导体器件结构及其制造方法

    公开(公告)号：US07512924B2

    公开(公告)日：2009-03-31

    申请号：US11333618

    申请日：2006-01-17

    申请人： Hsien-Wei Chen ,  Hsueh-Chung Chen ,  Yi-Lung Cheng ,  Shin-Puu Jeng

    发明人： Hsien-Wei Chen ,  Hsueh-Chung Chen ,  Yi-Lung Cheng ,  Shin-Puu Jeng

    IPC分类号： G06F17/50

    CPC分类号： H01L27/0203 ,  G06F17/5068 ,  G06F2217/12 ,  Y02P90/265

    摘要： A method of generating a layout for a semiconductor device array is provided. A first layout is provided, comprising an active conductive feature, a boundary area surrounding the active conductive feature, and an open area other than the active conductive feature and the boundary area. A plurality of dummy templates of different pattern densities are provided, each of which comprises a plurality of dummy seeds. A second layout is generated by adding the dummy seeds on the open area according to at least one of the dummy templates.

    摘要翻译： 提供了一种生成半导体器件阵列布局的方法。 提供了第一布局，包括有源导电特征，围绕有源导电特征的边界区域以及除了有源导电特征和边界区域之外的开放区域。 提供了多个不同图案密度的虚拟模板，每个虚拟模板包括多个虚拟种子。 通过根据至少一个虚拟模板将假种子添加到开放区域来生成第二布局。

    Novel device structure having enhanced surface adhesion and failure mode analysis
    32.
    发明申请
    Novel device structure having enhanced surface adhesion and failure mode analysis 有权
    具有增强的表面粘附性和故障模式分析的新型器件结构

    公开(公告)号：US20050272260A1

    公开(公告)日：2005-12-08

    申请号：US10861149

    申请日：2004-06-04

    申请人： Hway Lin ,  Yi-Lung Cheng ,  Chao-Hsiung Wang

    发明人： Hway Lin ,  Yi-Lung Cheng ,  Chao-Hsiung Wang

    IPC分类号： H01L21/44 ,  H01L21/768

    CPC分类号： H01L21/76802 ,  H01L2924/0002 ,  H01L2924/00

    摘要： A substrate is provided having semiconductor device structures formed in and on the substrate. The semiconductor device structures comprise conductor layers embedded in openings in dielectric layers having a dielectric constant of less than 4.5. The dielectric layer has a roughness between the dielectric and the conductor wherein the roughness of the dielectric layer divided by the thickness of a barrier layer underlying the conductor layer is 0 to 1. The integrated circuit structure is prepared for failure analysis by removing the low dielectric constant dielectric layers and exposing the conductor layers for further failure analysis by optical examination or scanning electron microscope (SEM).

    摘要翻译： 提供了一种衬底，其具有形成在衬底中和衬底上的半导体器件结构。 半导体器件结构包括嵌入介电常数小于4.5的电介质层的开口中的导体层。 电介质层在电介质和导体之间具有粗糙度，其中介电层的粗糙度除以导体层下面的阻挡层的厚度为0-1。集成电路结构通过去除低电介质来制备用于故障分析 恒电介质层，并通过光学检查或扫描电子显微镜（SEM）暴露导体层进行进一步的故障分析。

    Heat dissipation structure and method thereof
    33.
    发明申请
    Heat dissipation structure and method thereof 审中-公开
    散热结构及其方法

    公开(公告)号：US20050236716A1

    公开(公告)日：2005-10-27

    申请号：US10829583

    申请日：2004-04-22

    申请人： Hsuch-Chung Chen ,  Yi-Lung Cheng ,  Hsien-Wei Chen ,  Shin-Puu Jeng

    发明人： Hsuch-Chung Chen ,  Yi-Lung Cheng ,  Hsien-Wei Chen ,  Shin-Puu Jeng

    IPC分类号： H01L23/367 ,  H01L23/48 ,  H01L23/528

    CPC分类号： H01L23/5286 ,  H01L23/3677 ,  H01L2924/0002 ,  H01L2924/00

    摘要： A semiconductor structure and method for dissipating heat away from a semiconductor device having a plurality of power lines is provided. The semiconductor structure includes a semiconductor substrate and a plurality of interconnect structures disposed on the substrate and in contact therewith and extending through the semiconductor device, the interconnect structures for dissipating heat to the substrate. Each of the plurality of interconnect structures comprises at least one via stack.

    摘要翻译： 提供了一种半导体结构和方法，用于从具有多个电源线的半导体器件散发热量。 半导体结构包括半导体衬底和布置在衬底上并与其接触并延伸穿过半导体器件的多个互连结构，用于将热量散发到衬底的互连结构。 多个互连结构中的每一个包括至少一个通孔堆叠。

    Novel nitride barrier layer to prevent metal (Cu) leakage issue in a dual damascene structure
    34.
    发明申请
    Novel nitride barrier layer to prevent metal (Cu) leakage issue in a dual damascene structure 有权
    新型氮化物阻挡层，以防止双镶嵌结构中的金属（Cu）泄漏问题

    公开(公告)号：US20050153537A1

    公开(公告)日：2005-07-14

    申请号：US10753637

    申请日：2004-01-08

    申请人： Yi-Lung Cheng ,  Ying-Lung Wang

    发明人： Yi-Lung Cheng ,  Ying-Lung Wang

    IPC分类号： H01L21/4763 ,  H01L21/768 ,  H01L23/52

    CPC分类号： H01L21/76832 ,  H01L21/76807 ,  H01L21/76826

    摘要： A method for forming a composite barrier layer that also functions as an etch stop in a damascene process is disclosed. A SiC layer is deposited on a substrate in a CVD process chamber followed by deposition of a silicon nitride layer to complete the composite barrier layer. The SiC layer exhibits excellent adhesion to a copper layer in the substrate and is formed by a method that avoids reactive Si+4 species and thereby prevents CuSiX formation. The silicon nitride layer thickness is sufficient to provide superior barrier capability to metal ions but is kept as thin as possible to minimize the dielectric constant of the composite barrier layer. The composite barrier layer provides excellent resistance to copper oxidation during oxygen ashing steps and enables a copper layer to be fabricated with a lower leakage current than when a conventional silicon nitride barrier layer is employed.

    摘要翻译： 公开了一种用于形成复合阻挡层的方法，该复合阻挡层也用作镶嵌工艺中的蚀刻停止。 将SiC层沉积在CVD处理室中的衬底上，随后沉积氮化硅层以完成复合势垒层。 SiC层对衬底中的铜层表现出优异的粘附性，并且通过避免反应性Si + 4+物质并由此防止CuSi X X形成的方法形成。 氮化硅层的厚度足以为金属离子提供优异的阻挡能力，但保持尽可能的薄，以使复合阻挡层的介电常数最小化。 复合阻挡层在氧化灰化步骤期间提供优异的铜氧化性能，并且与使用常规氮化硅阻挡层相比，能够以较低的漏电流制造铜层。

    Method for improved cleaning in HDP-CVD process with reduced NF3 usage
    35.
    发明授权
    Method for improved cleaning in HDP-CVD process with reduced NF3 usage 有权
    改善HDP-CVD工艺清洗方法，减少NF3使用的方法

    公开(公告)号：US06584987B1

    公开(公告)日：2003-07-01

    申请号：US09808929

    申请日：2001-03-16

    申请人： Yi-Lung Cheng ,  Chun-Ching Tsan ,  Wen-Kung Cheng ,  Yin-Lang Wang

    发明人： Yi-Lung Cheng ,  Chun-Ching Tsan ,  Wen-Kung Cheng ,  Yin-Lang Wang

    IPC分类号： B08B704

    CPC分类号： H01J37/32862 ,  B08B7/0035 ,  C23C16/4405 ,  Y10S438/905

    摘要： A method for cleaning residual material from a chemical vapor deposition (CVD) apparatus in situ employing dry etching. There is first employed a high density plasma chemical vapor deposition (HDP-CVD) method to deposit layers of silicon oxide material upon substrates within a chemical vapor deposition reactor apparatus. After removal of substrates, the reactor chamber is closed off. The interior of the reactor is then filled with a gas and a plasma formed therewithin, to which oxygen is added and the reactor allowed to come to an increased temperature and bake for a period of time. The reactor power is then turned off and the reactor evacuated. There is then carried out a normal cleaning step within the reactor chamber employing a reactive gas such as NF3, with greater cleaning efficiency due to the increased temperature caused by the baking step.

    摘要翻译： 一种从化学气相沉积（CVD）装置中原位采用干法蚀刻来清除残余物质的方法。 首先采用高密度等离子体化学气相沉积（HDP-CVD）方法在化学气相沉积反应器装置中的衬底上沉积氧化硅材料层。 在移除基板之后，关闭反应室。 然后将反应器的内部填充有在其中形成的气体和等离子体，向其中加入氧并使反应器升温并烘烤一段时间。 然后关闭反应堆功率，反应器排空。 然后，使用反应气体如NF3在反应器室内进行正常的清洗步骤，由于烘烤步骤引起的温度升高，清洗效率更高。

    Nitride barrier layer to prevent metal (Cu) leakage issue in a dual damascene structure
    37.
    发明授权
    Nitride barrier layer to prevent metal (Cu) leakage issue in a dual damascene structure 有权
    氮化物阻挡层，以防止双重镶嵌结构中的金属（Cu）泄漏问题

    公开(公告)号：US07176571B2

    公开(公告)日：2007-02-13

    申请号：US10753637

    申请日：2004-01-08

    申请人： Yi-Lung Cheng ,  Ying-Lung Wang

    发明人： Yi-Lung Cheng ,  Ying-Lung Wang

    IPC分类号： H01L23/48 ,  H01L23/52 ,  H01L29/40

    CPC分类号： H01L21/76832 ,  H01L21/76807 ,  H01L21/76826

    摘要： A method for forming a composite barrier layer that also functions as an etch stop in a damascene process is disclosed. A SiC layer is deposited on a substrate in a CVD process chamber followed by deposition of a silicon nitride layer to complete the composite barrier layer. The SiC layer exhibits excellent adhesion to a copper layer in the substrate and is formed by a method that avoids reactive Si+4 species and thereby prevents CuSiX formation. The silicon nitride layer thickness is sufficient to provide superior barrier capability to metal ions but is kept as thin as possible to minimize the dielectric constant of the composite barrier layer. The composite barrier layer provides excellent resistance to copper oxidation during oxygen ashing steps and enables a copper layer to be fabricated with a lower leakage current than when a conventional silicon nitride barrier layer is employed.

    摘要翻译： 公开了一种用于形成复合阻挡层的方法，该复合阻挡层也用作镶嵌工艺中的蚀刻停止。 将SiC层沉积在CVD处理室中的衬底上，随后沉积氮化硅层以完成复合势垒层。 SiC层对衬底中的铜层表现出优异的粘附性，并且通过避免反应性Si + 4+物质并由此防止CuSi X X形成的方法形成。 氮化硅层的厚度足以为金属离子提供优异的阻挡能力，但保持尽可能的薄，以使复合阻挡层的介电常数最小化。 复合阻挡层在氧化灰化步骤期间提供优异的铜氧化性能，并且与使用常规氮化硅阻挡层相比，能够以较低的漏电流制造铜层。

    Device structure having enhanced surface adhesion and failure mode analysis
    38.
    发明授权
    Device structure having enhanced surface adhesion and failure mode analysis 有权
    具有增强的表面粘附和破坏模式分析的装置结构

    公开(公告)号：US07157367B2

    公开(公告)日：2007-01-02

    申请号：US10861149

    申请日：2004-06-04

    申请人： Hway Chi Lin ,  Yi-Lung Cheng ,  Chao-Hsiung Wang

    发明人： Hway Chi Lin ,  Yi-Lung Cheng ,  Chao-Hsiung Wang

    IPC分类号： H01L21/4763

    CPC分类号： H01L21/76802 ,  H01L2924/0002 ,  H01L2924/00

    摘要： A substrate is provided having semiconductor device structures formed in and on the substrate. The semiconductor device structures comprise conductor layers embedded in openings in dielectric layers having a dielectric constant of less than 4.5. The dielectric layer has a roughness between the dielectric and the conductor wherein the roughness of the dielectric layer divided by the thickness of a barrier layer underlying the conductor layer is 0 to 1. The integrated circuit structure is prepared for failure analysis by removing the low dielectric constant dielectric layers and exposing the conductor layers for further failure analysis by optical examination or scanning electron microscope (SEM).

    摘要翻译： 提供了一种衬底，其具有形成在衬底中和衬底上的半导体器件结构。 半导体器件结构包括嵌入介电常数小于4.5的电介质层的开口中的导体层。 电介质层在电介质和导体之间具有粗糙度，其中介电层的粗糙度除以导体层下面的阻挡层的厚度为0-1。集成电路结构通过去除低电介质来制备用于故障分析 恒电介质层，并通过光学检查或扫描电子显微镜（SEM）暴露导体层进行进一步的故障分析。