公开(公告)号：US5440509A

公开(公告)日：1995-08-08

申请号：US22392

申请日：1993-02-24

申请人： Masaki Momodomi ,  Koichi Toita ,  Yasuo Itoh ,  Yoshihisa Iwata ,  Fujio Masuoka ,  Masahiko Chiba ,  Tetsuo Endo ,  Riichiro Shirota ,  Ryouhei Kirisawa

发明人： Masaki Momodomi ,  Koichi Toita ,  Yasuo Itoh ,  Yoshihisa Iwata ,  Fujio Masuoka ,  Masahiko Chiba ,  Tetsuo Endo ,  Riichiro Shirota ,  Ryouhei Kirisawa

IPC分类号： G11C17/00 ,  G11C16/02 ,  G11C16/04 ,  G11C16/06 ,  G11C16/08 ,  G11C16/30 ,  H01L27/115

CPC分类号： G11C16/0483 ,  G11C16/08 ,  G11C16/30 ,  H01L27/115

摘要： An erasable programmable read-only memory (EPROM) with a NAND cell structure includes NAND cell blocks, each of which has a selection transistor connected to the corresponding bit line and memory cell transistors connected in series. Word lines are connected to control gates of the cell transistors. In a data write mode, a selection transistor of a certain cell block containing a selected cell is rendered conductive to connect the cell block to the corresponding bit line. A control circuit is provided for applying an "L" level voltage (approximately 0 V) to a word line connected to the selected cell, applying an "H" level voltage (approximately 20 V) to a word line or word lines positioned between the selected word line and a contact node connecting the cell block and a specific bit line associated therewith, applying a voltage corresponding to data to be written to the specific bit line, and applying an intermediate voltage between the "H" and "L" level voltages to non-selected bit lines, thereby writing the data in the selected cell by tunneling. If the data is logic "0" data, the intermediate voltage is applied also to the specific bit line.

摘要翻译： 具有NAND单元结构的可擦除可编程只读存储器（EPROM）包括NAND单元块，每个单元块具有连接到相应位线的选择晶体管和串联连接的存储单元晶体管。 字线连接到单元晶体管的控制栅极。 在数据写入模式中，包含所选择的单元的某个单元块的选择晶体管被导通以将单元块连接到对应的位线。 提供一种控制电路，用于向连接到所选择的单元的字线施加“L”电平电压（大约0V），对位于第一个单元之间的字线或字线施加“H”电平电压（大约20V） 选择字线和连接单元块和与其相关联的特定位线的接触节点，施加与要写入到特定位线的数据相对应的电压，以及在“H”和“L”电平电压之间施加中间电压 到未选择的位线，从而通过隧道将数据写入所选择的单元。 如果数据是逻辑“0”数据，则中间电压也被施加到特定位线。

公开(公告)号：US5327395A

公开(公告)日：1994-07-05

申请号：US957000

申请日：1992-10-06

申请人： Yoshihisa Sugiura ,  Yoshihisa Iwata ,  Masaki Momodomi ,  Yasuo Itoh ,  Tomoharu Tanaka ,  Yoshiyuki Tanaka

发明人： Yoshihisa Sugiura ,  Yoshihisa Iwata ,  Masaki Momodomi ,  Yasuo Itoh ,  Tomoharu Tanaka ,  Yoshiyuki Tanaka

IPC分类号： G11C17/00 ,  G11C16/02 ,  G11C16/08 ,  G11C16/10 ,  G11C8/00

CPC分类号： G11C16/08 ,  G11C16/10 ,  G11C2216/14

摘要： A NOR operation is performed on the address bit by bit by a NOR circuit, and when the final address in a page is detected from the result of the NOR operation by a final address detection circuit, a program starting circuit executes data writing to a memory cell. This can ensure detection of the final address in a page without using a counter circuit. It is therefore possible to simplify the structure of the final address detection circuit and reduce the circuit area occupying in a semiconductor memory device.

摘要翻译： 通过NOR电路对地址逐位执行NOR运算，并且当由最终地址检测电路从NOR运算的结果检测到页面中的最终地址时，程序启动电路执行向存储器的数据写入 细胞。 这可以确保在不使用计数器电路的情况下检测页面中的最终地址。 因此，可以简化最终地址检测电路的结构并减少半导体存储器件占用的电路面积。

公开(公告)号：US5280454A

公开(公告)日：1994-01-18

申请号：US764213

申请日：1991-09-23

申请人： Tomoharu Tanaka ,  Yoshihisa Iwata ,  Koji Sakui ,  Masaki Momodomi

发明人： Tomoharu Tanaka ,  Yoshihisa Iwata ,  Koji Sakui ,  Masaki Momodomi

IPC分类号： G11C16/02 ,  G11C16/04 ,  G11C16/06 ,  G11C16/16 ,  H01L21/8247 ,  H01L27/115 ,  H01L29/788 ,  H01L29/792

CPC分类号： G11C16/16

摘要： An EEPROM includes an array of memory cells divided into a plurality of memory blocks in a semiconductor well region in a substrate. Each block includes series arrays of FATMOS transistors each acting as one memory cell, wherein binary information may be stored in a selected cell transistor by causing carriers to tunnel between the floating gate thereof and the well region. In each block, word lines are connected to the control gates of cell transistors; control lines are to select transistors provided in the series arrays of cell transistors, with which bit lines are associated. A block-erase operation is performed such that a desired one of the memory blocks is selected for erase, while forcing the remaining memory blocks to remain non-erased. To do this, a first voltage is applied to those of the word lines of the selected block, while applying a second voltage to the remaining word lines of the non-selected blocks, the control lines of all the blocks, and the well region.

摘要翻译： EEPROM包括在衬底中的半导体阱区中被划分成多个存储块的存储器单元的阵列。 每个块包括作为一个存储单元的FATMOS晶体管的串联阵列，其中二进制信息可以通过使载流子在其浮动栅极和阱区域之间隧穿而存储在所选择的单元晶体管中。 在每个块中，字线连接到单元晶体管的控制栅极; 控制线是选择提供在单元晶体管的串联阵列中的晶体管，与其相关联的位线。 执行块擦除操作，使得所选择的一个存储块被选择用于擦除，同时强制剩余的存储块保持不被擦除。 为此，将第一电压施加到所选块的字线的第一电压，同时对未选块的剩余字线，所有块的控制线和阱区施加第二电压。

公开(公告)号：US5179427A

公开(公告)日：1993-01-12

申请号：US869123

申请日：1992-04-15

申请人： Ryozo Nakayama ,  Riichiro Shirota ,  Yasuo Itoh ,  Ryouhei Kirisawa ,  Hideko Odaira ,  Masaki Momodomi ,  Yoshihisa Iwata ,  Tomoharu Tanaka ,  Seiichi Aritome ,  Tetsuo Endoh ,  Fujio Masuoka

发明人： Ryozo Nakayama ,  Riichiro Shirota ,  Yasuo Itoh ,  Ryouhei Kirisawa ,  Hideko Odaira ,  Masaki Momodomi ,  Yoshihisa Iwata ,  Tomoharu Tanaka ,  Seiichi Aritome ,  Tetsuo Endoh ,  Fujio Masuoka

IPC分类号： G11C16/04 ,  H01L27/115

CPC分类号： H01L27/115 ,  G11C16/0483

摘要： A NAND cell type EEPROM has parallel data transmission lines formed above a substrate, and a memory cell section including a plurality of NAND type cell units containing a NAND type cell unit that is associated with a certain bit line of the bit lines. This NAND type cell unit has a series-circuit of a preselected number of data storage transistors with control gates, and a selection transistor. A substrate voltage-stabilizing layer is insulatively provided above the substrate and positioned in the field area in adjacent to the certain bit line. The conductive layer is connected to the substrate by a contact portion so that the substrate voltage can be constantly set to a preselected voltage potential of a fixed value during the NAND type cell unit is being subjected to the write and erase modes.

摘要翻译： NAND单元型EEPROM具有形成在衬底上的并行数据传输线，以及存储单元部分，其包括与位线的某个位线相关联的NAND型单元单元的多个NAND型单元单元。 该NAND型单元单元具有预选数量的具有控制栅极的数据存储晶体管和选择晶体管的串联电路。 衬底电压稳定层被绝缘地设置在衬底之上并且位于与某一位线相邻的场区中。 导电层通过接触部分连接到基板，使得在对NAND型单元单元进行写入和擦除模式期间，基板电压可以恒定地设定为固定值的预选电压电位。

公开(公告)号：US5075890A

公开(公告)日：1991-12-24

申请号：US516311

申请日：1990-04-30

申请人： Yasuo Itoh ,  Masaki Momodomi ,  Yoshihisa Iwata ,  Tomoharu Tanaka ,  Fujio Masuoka

发明人： Yasuo Itoh ,  Masaki Momodomi ,  Yoshihisa Iwata ,  Tomoharu Tanaka ,  Fujio Masuoka

IPC分类号： G11C16/08 ,  G11C16/12 ,  G11C16/30

CPC分类号： G11C16/08 ,  G11C16/12 ,  G11C16/30

摘要： An electrically erasable programmable read-only memory has memory cell blocks, each of which has NAND type cell units associated with the bit lines respectively. Each cell unit has a series-circuit of floating gate type memory cell transistors and a selection transistor provided between the corresponding bit line and the series-circuit of memory cell transistors. A row decoder is provided in common to the memory cell blocks, for generating an "H" level voltage which is supplied to a selection gate control line connected to the selection transistor and to a selected word line or lines in a cell unit. A voltage boost circuit is provided for every memory cell block, for causing the "H" level voltage to increase up to a preselected potential level which is high enough to render the cell transistors conductive. The voltage boost circuit includes a first booster section for the selection gate control line, and a second section for the word lines. The second section operates in response to the output voltage of the first section.

摘要翻译： 电可擦除可编程只读存储器具有存储单元块，每个存储单元块分别具有与位线相关联的NAND型单元单元。 每个单元单元具有浮置型存储单元晶体管的串联电路和设置在相应位线和存储单元晶体管的串联电路之间的选择晶体管。 向存储单元块共同地提供行解码器，用于产生提供给连接到选择晶体管的选择栅极控制线和单元单元中所选择的字线或线的“H”电平电压。 为每个存储器单元块提供升压电路，用于使“H”电平电压增加到足以使单元晶体管导通的预选电位电平。 升压电路包括用于选择栅极控制线的第一升压部分和用于字线的第二部分。 第二部分响应于第一部分的输出电压而工作。

公开(公告)号：US09293175B2

公开(公告)日：2016-03-22

申请号：US13607493

申请日：2012-09-07

申请人： Katsuaki Sakurai ,  Yoshihisa Iwata

发明人： Katsuaki Sakurai ,  Yoshihisa Iwata

IPC分类号： G11C16/30 ,  G11C5/14

CPC分类号： G11C5/147 ,  G11C16/30

摘要： A semiconductor memory device includes a first comparative device, to which first and second voltages are input; a first capacitor, which accumulates the electrical potential of a first node; a power source, which outputs the first electric current to a second node; a resistor, which generates a third voltage in the second node; a second capacitor, which accumulates the electric potential of the second node; first switches, which make a common connection at a third node possible for the first node and the second node, to which the first capacitor and the second capacitor are connected respectively; and a second comparison device, which uses as an input voltage a fourth voltage, which is obtained as a result of the charge share between the first and the second capacitors and the electrical potential of a fourth node, and equalizes the electrical potential of the fourth node with the fourth voltage.

摘要翻译： 半导体存储器件包括第一和第二电压输入的第一比较器件; 第一电容器，其累积第一节点的电位; 电源，其将第一电流输出到第二节点; 电阻器，其在第二节点中产生第三电压; 累积第二节点的电位的第二电容器; 第一开关，其在第一节点和第二节点分别连接到第一节点和第二节点的第三节点处形成公共连接; 以及第二比较装置，其将作为第一和第二电容器之间的电荷共享的结果获得的第四电压用作输入电压和第四节点的电位，并且使第四电压的电位相等 节点具有第四电压。

公开(公告)号：US08861279B2

公开(公告)日：2014-10-14

申请号：US13605840

申请日：2012-09-06

申请人： Tomoo Hishida ,  Yoshihisa Iwata

发明人： Tomoo Hishida ,  Yoshihisa Iwata

IPC分类号： G11C11/34

CPC分类号： G11C16/0483 ,  G11C16/06 ,  G11C16/30 ,  H01L27/1157 ,  H01L27/11582 ,  H01L29/7926

摘要： A semiconductor storage device has a nonvolatile storage region, a voltage generating circuit that generates an operational voltage for the storage region, and a control circuit that sends the voltage generated by the voltage generating circuit to the storage region. The voltage generating circuit has a transistor, a first resistance element, a second resistance element, and a comparator. The first resistance element and the second resistance element have wiring structure for resistance. The resistance wiring in the wiring structure has the same line width as the finest line width in the wiring formed in the storage region.

摘要翻译： 半导体存储装置具有非易失性存储区域，产生用于存储区域的工作电压的电压产生电路以及将由电压产生电路产生的电压发送到存储区域的控制电路。 电压产生电路具有晶体管，第一电阻元件，第二电阻元件和比较器。 第一电阻元件和第二电阻元件具有用于电阻的布线结构。 布线结构中的电阻布线具有与形成在存储区域中的布线中的最细线宽度相同的线宽。

公开(公告)号：US08797777B2

公开(公告)日：2014-08-05

申请号：US13423546

申请日：2012-03-19

申请人： Tomoo Hishida ,  Yoshihisa Iwata

发明人： Tomoo Hishida ,  Yoshihisa Iwata

IPC分类号： G11C5/02

CPC分类号： H01L27/11582 ,  G11C5/025 ,  G11C5/04 ,  G11C5/063 ,  G11C7/18 ,  G11C8/12 ,  G11C16/0483 ,  G11C2213/71 ,  H01L23/528 ,  H01L27/10 ,  H01L27/11568 ,  H01L27/11575 ,  H01L29/7926 ,  H01L2924/0002 ,  H01L2924/00

摘要： A semiconductor memory device comprises: a semiconductor substrate; a plurality of memory units provided on the semiconductor substrate and each including a plurality of memory cells that are stacked; and a plurality of bit lines formed above each of a plurality of the memory units aligned in a column direction, an alignment pitch in a row direction of the plurality of bit lines being less than an alignment pitch in the row direction of the memory units, and an end of each of the memory units aligned in the column direction being connected to one of the plurality of bit lines formed above the plurality of the memory units aligned in the column direction.

摘要翻译： 半导体存储器件包括：半导体衬底; 多个存储单元，设置在所述半导体衬底上，并且每个存储单元包括堆叠的多个存储单元; 以及多个位线形成在沿列方向排列的多个存储器单元中的每一个上，多个位线的行方向上的对准间距小于存储单元的行方向上的对准间距， 并且在列方向上排列的每个存储单元的一端连接到形成在沿列方向排列的多个存储单元上的多个位线之一。

公开(公告)号：US20130258796A1

公开(公告)日：2013-10-03

申请号：US13607529

申请日：2012-09-07

申请人： Takeshi Hioka ,  Yoshihisa Iwata

发明人： Takeshi Hioka ,  Yoshihisa Iwata

IPC分类号： G11C5/14

CPC分类号： G11C7/222 ,  G11C5/063 ,  G11C5/145 ,  G11C16/10

摘要： A semiconductor device comprising a stacked layer memory block and associated peripheral circuits in stacked layer arrangements. Booster circuits in a variety of stacked layer arrangements are described. The booster circuit possesses plural rectifier cells that are series-connected and plural first capacitors. The plural first capacitors receive the first clock signal on one end, and the other ends are each connected to one end of different rectifier cells. The first capacitor is composed of capacities between plural first conductive layers that are arrayed with a set pitch perpendicularly to the substrate. One of the either even numbered or odd numbered first conductive layers is supplied with a first clock signal. The other of the either even numbered or odd numbered first conductive layers that line perpendicularly to the substrate is, individually, connected to one end of different rectifier cells.

摘要翻译： 一种半导体器件，包括堆叠层存储块和堆叠层布置中的相关外围电路。 描述了各种堆叠层布置中的加强电路。 升压电路具有串联连接的多个整流单元和多个第一电容器。 多个第一电容器在一端接收第一时钟信号，另一端分别连接到不同整流器单元的一端。 第一电容器由以与衬底垂直的设定间距排列的多个第一导电层之间的电容构成。 偶数或奇数编号的第一导电层中的一个被提供有第一时钟信号。 垂直于衬底的偶数或奇数的第一导电层中的另一个单独连接到不同整流器单元的一端。

公开(公告)号：US08456887B2

公开(公告)日：2013-06-04

申请号：US12746866

申请日：2008-09-09

申请人： Yoshihisa Iwata

发明人： Yoshihisa Iwata

IPC分类号： G11C7/12

CPC分类号： G11C11/5614 ,  G11C13/0009 ,  G11C13/0011 ,  G11C13/004 ,  G11C13/0064 ,  G11C13/0069 ,  G11C2013/0054 ,  G11C2013/0078 ,  G11C2013/009 ,  G11C2213/71 ,  G11C2213/72

摘要： A nonvolatile semiconductor memory device comprises a cell array having plural memory cells arranged in matrix, each memory cell including a variable resistor having a resistance reversibly variable to store data corresponding to the resistance of the variable resistor; a selection circuit operative to select a memory cell from the cell array; and a write circuit operative to execute certain voltage or current supply to the memory cell selected by the selection circuit to vary the resistance of a variable resistor in the selected memory cell to erase or write data. The write circuit terminates the voltage or current supply to the selected memory cell in accordance with resistance variation situation of the variable resistor in the selected memory cell when current flowing in the selected memory cell reaches a certain level appeared after the data erase or write.

摘要翻译： 非易失性半导体存储器件包括具有以矩阵形式排列的多个存储单元的单元阵列，每个存储单元包括具有可逆可变电阻的可变电阻器，用于存储对应于可变电阻器的电阻的数据; 选择电路，用于从所述单元阵列中选择存储单元; 以及写入电路，用于对由选择电路选择的存储器单元执行一定的电压或电流供应，以改变所选择的存储器单元中的可变电阻器的电阻以擦除或写入数据。 写入电路在数据擦除或写入后出现在选定的存储单元中流动的电流达到一定程度时，根据所选存储单元中的可变电阻器的电阻变化情况，终止对所选存储单元的电压或电流供应。