公开(公告)号：US20110316123A1

公开(公告)日：2011-12-29

申请号：US12801837

申请日：2010-06-28

申请人： Yoshitaka Sasaki ,  Hiroyuki Ito ,  Atsushi Iijima

发明人： Yoshitaka Sasaki ,  Hiroyuki Ito ,  Atsushi Iijima

IPC分类号： H01L23/544 ,  H01L21/78

CPC分类号： H01L25/0657 ,  H01L21/563 ,  H01L21/6835 ,  H01L23/522 ,  H01L23/528 ,  H01L24/03 ,  H01L24/05 ,  H01L24/24 ,  H01L24/25 ,  H01L24/29 ,  H01L24/32 ,  H01L24/82 ,  H01L24/83 ,  H01L24/92 ,  H01L24/94 ,  H01L24/95 ,  H01L24/96 ,  H01L25/50 ,  H01L2221/68327 ,  H01L2221/6834 ,  H01L2224/0231 ,  H01L2224/02311 ,  H01L2224/02313 ,  H01L2224/02317 ,  H01L2224/02321 ,  H01L2224/02371 ,  H01L2224/02375 ,  H01L2224/02379 ,  H01L2224/02381 ,  H01L2224/0239 ,  H01L2224/03444 ,  H01L2224/0345 ,  H01L2224/0346 ,  H01L2224/0392 ,  H01L2224/04026 ,  H01L2224/05008 ,  H01L2224/05644 ,  H01L2224/05647 ,  H01L2224/24011 ,  H01L2224/24146 ,  H01L2224/245 ,  H01L2224/2919 ,  H01L2224/32145 ,  H01L2224/32148 ,  H01L2224/82005 ,  H01L2224/821 ,  H01L2224/82101 ,  H01L2224/82106 ,  H01L2224/83005 ,  H01L2224/83121 ,  H01L2224/8313 ,  H01L2224/83191 ,  H01L2224/83193 ,  H01L2224/83203 ,  H01L2224/83815 ,  H01L2224/8385 ,  H01L2224/9202 ,  H01L2224/92244 ,  H01L2224/95001 ,  H01L2224/97 ,  H01L2225/06565 ,  H01L2924/01029 ,  H01L2924/07802 ,  H01L2924/14 ,  H01L2924/00

摘要： In a laminated semiconductor substrate, a plurality of semiconductor substrates are laminated. Each of the semiconductor substrate has a plurality of scribe-groove parts formed along scribe lines. Further, each of the semiconductor substrate has a plurality of device regions insulated from each other and has a semiconductor device formed therein, a first wiring electrode and a second wiring electrode extend to the inside of a interposed groove part from a first device region and a second device region respectively, and are separated from each other. In the laminated semiconductor substrate, a through hole which the first wiring electrode appears is formed. The laminated semiconductor substrate has a through electrode. The through electrode is contact with all of the first wiring electrodes appearing in the through hole. The laminated semiconductor substrate has a plurality of laminated chip regions.

摘要翻译： 在层叠半导体衬底中层叠多个半导体衬底。 每个半导体衬底具有沿着划线形成的多个划线槽部分。 此外，每个半导体衬底具有彼此绝缘的多个器件区域，并且其中形成有半导体器件，第一布线电极和第二布线电极从第一器件区域延伸到插入的沟槽部分的内部，并且 第二装置区域，并且彼此分离。 在层叠半导体基板中，形成有第一配线电极的通孔。 层叠半导体基板具有贯通电极。 通孔与通孔中出现的所有第一布线电极接触。 层叠半导体衬底具有多个层叠芯片区域。

公开(公告)号：US08077433B2

公开(公告)日：2011-12-13

申请号：US12132368

申请日：2008-06-03

申请人： Yoshitaka Sasaki ,  Hiroyuki Ito ,  Atsushi Iijima

发明人： Yoshitaka Sasaki ,  Hiroyuki Ito ,  Atsushi Iijima

IPC分类号： G11B5/17

CPC分类号： G11B5/3116 ,  G11B5/1278 ,  G11B5/3163

摘要： A thin-film magnetic head is constructed such that a main magnetic pole layer having a magnetic pole end face on a side of a medium-opposing surface opposing a recording medium, a write shield layer opposing the main magnetic pole layer on the medium-opposing surface side, a gap layer formed between the main magnetic pole layer and write shield layer, and a thin-film coil wound about the write shield layer or main magnetic pole layer are laminated on a substrate. This thin-film magnetic head has an equidistant two-stage structure in which a first turn part of a first conductor layer and a second turn part of a second conductor layer overlap vertically along the medium-opposing surface while having the same front distance from respective front side faces closer to the medium-opposing surface to the medium-opposing surface.

摘要翻译： 薄膜磁头被构造成使得在与介质相对的介质相对表面的侧面上具有磁极端面的主磁极层，与介质相对的主磁极层相对的写入屏蔽层 在主磁极层和写入屏蔽层之间形成的间隙层和缠绕在写入屏蔽层或主磁极层上的薄膜线圈层叠在基板上。 这种薄膜磁头具有等距离的两级结构，其中第一导体层的第一匝部分和第二导体层的第二匝部分沿着介质相对表面垂直重叠，同时具有与其相同的前部距离 前侧面靠近与介质相对表面的介质相对表面。

公开(公告)号：US20110228417A1

公开(公告)日：2011-09-22

申请号：US12727620

申请日：2010-03-19

申请人： Yoshitaka Sasaki ,  Hiroyuki Ito ,  Shigeki Tanemura ,  Hironori Araki ,  Atsushi Iijima

发明人： Yoshitaka Sasaki ,  Hiroyuki Ito ,  Shigeki Tanemura ,  Hironori Araki ,  Atsushi Iijima

IPC分类号： G11B5/02

CPC分类号： G11B5/314 ,  G11B5/3163 ,  G11B5/6088 ,  G11B2005/001 ,  G11B2005/0021

摘要： A near-field light generating element has an outer surface. The outer surface includes a bottom surface, first and second inclined surfaces, an edge part that connects the first and second inclined surfaces to each other, and a front end face located in a medium facing surface. The front end face includes a first side that lies at an end of the first inclined surface, a second side that lies at an end of the second inclined surface, and a tip that is formed by contact of the first and second sides with each other and forms a near-field light generating part. Each of the first side and the second side has a lower part and an upper part that are continuous with each other. An angle formed between the upper part of the first side and the upper part of the second side is smaller than that formed between the lower part of the first side and the lower part of the second side.

摘要翻译： 近场光产生元件具有外表面。 外表面包括底面，第一和第二倾斜表面，将第一和第二倾斜表面彼此连接的边缘部分和位于介质面向表面中的前端面。 前端面包括位于第一倾斜面的端部的第一侧，位于第二倾斜面的端部的第二侧和通过第一和第二侧面彼此接触形成的前端部 并形成近场光产生部。 第一侧和第二侧中的每一个具有彼此连续的下部和上部。 形成在第一侧的上部和第二侧的上部之间的角度小于在第一侧的下部和第二侧的下部之间形成的角度。

公开(公告)号：US20110186985A1

公开(公告)日：2011-08-04

申请号：US12656458

申请日：2010-01-29

申请人： Yoshitaka Sasaki ,  Hiroyuki Ito ,  Atsushi Iijima

发明人： Yoshitaka Sasaki ,  Hiroyuki Ito ,  Atsushi Iijima

IPC分类号： H01L23/498 ,  H01L23/28 ,  H01L21/768 ,  H01L21/50

CPC分类号： H01L21/50 ,  H01L21/768 ,  H01L23/28 ,  H01L23/498 ,  H01L2224/16145

摘要： A semiconductor substrate has a plurality of groove portions formed along scribe lines. The semiconductor substrate includes: a unit region in contact with at least any one of the plurality of groove portions; and a wiring electrode with a portion thereof arranged within the unit region. Further, the plurality of groove portions have a wide-port structure in which a wide width portion wider in width than a groove lower portion including a bottom portion is formed at an inlet port thereof.

摘要翻译： 半导体基板具有沿划线形成的多个槽部。 半导体衬底包括：与所述多个沟槽部分中的至少任一个接触的单位区域; 以及布线电极，其部分布置在单元区域内。 此外，多个槽部具有宽口结构，其宽度在宽度方面比包括底部的槽下部宽的部分形成在其入口处。

公开(公告)号：US20110095414A1

公开(公告)日：2011-04-28

申请号：US12588659

申请日：2009-10-22

申请人： Yoshitaka Sasaki ,  Hiroyuki Ito ,  Atsushi Iijima

发明人： Yoshitaka Sasaki ,  Hiroyuki Ito ,  Atsushi Iijima

IPC分类号： H01L23/52 ,  H01L23/48 ,  H01L21/60

CPC分类号： H01L25/0652 ,  H01L21/56 ,  H01L23/3114 ,  H01L24/05 ,  H01L24/24 ,  H01L24/29 ,  H01L24/32 ,  H01L24/82 ,  H01L24/96 ,  H01L2221/68377 ,  H01L2224/02166 ,  H01L2224/0401 ,  H01L2224/05554 ,  H01L2224/13022 ,  H01L2224/16 ,  H01L2224/18 ,  H01L2224/73267 ,  H01L2225/06551 ,  H01L2924/01006 ,  H01L2924/01015 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/01078 ,  H01L2924/01082 ,  H01L2924/07802 ,  H01L2924/14 ,  H01L2924/30105 ,  H01L2924/00

摘要： A semiconductor substrate has a plurality of groove portions formed along scribe lines. The semiconductor substrate includes: a device region in contact with at least any one of the plurality of groove portions and having a semiconductor device formed therein; a surface insulating layer formed to cover the device region and constituting a surface layer of the semiconductor substrate; and a wiring electrode connected to the semiconductor device and formed in a protruding shape rising above a surface of the surface insulating layer. The semiconductor substrate can be manufactured by forming a plurality of groove portions along scribe lines; applying an insulating material to a surface on a side where the plurality of groove portions are formed to form a surface insulating layer; and forming a wiring electrode connected to the semiconductor device and in a protruding shape rising above a surface of the surface insulating layer, after the formation of the surface insulating layer.

摘要翻译： 半导体基板具有沿划线形成的多个槽部。 半导体衬底包括：与多个沟槽部分中的至少一个接触并且具有形成在其中的半导体器件的器件区域; 形成为覆盖所述器件区域并构成所述半导体衬底的表面层的表面绝缘层; 以及连接到所述半导体器件并且形成为在所述表面绝缘层的表面上方上升的突出形状的布线电极。 可以通过沿划线形成多个槽部来制造半导体衬底; 将绝缘材料施加到形成所述多个槽部的一侧的表面上以形成表面绝缘层; 以及在形成所述表面绝缘层之后，形成连接到所述半导体器件并且以表面绝缘层的表面上方突出的形状的布线电极。

公开(公告)号：US08912042B2

公开(公告)日：2014-12-16

申请号：US13621540

申请日：2012-09-17

申请人： Yoshitaka Sasaki ,  Hiroyuki Ito ,  Atsushi Iijima ,  Ryuji Fujii

发明人： Yoshitaka Sasaki ,  Hiroyuki Ito ,  Atsushi Iijima ,  Ryuji Fujii

IPC分类号： H01L21/00 ,  H01L21/46 ,  H01L21/44

CPC分类号： H01L24/96 ,  H01L21/6835 ,  H01L22/22 ,  H01L24/24 ,  H01L24/94 ,  H01L25/0657 ,  H01L25/105 ,  H01L25/50 ,  H01L2221/68327 ,  H01L2221/6834 ,  H01L2224/24145 ,  H01L2224/32145 ,  H01L2224/83005 ,  H01L2224/94 ,  H01L2225/06524 ,  H01L2225/06527 ,  H01L2225/06551 ,  H01L2225/06565 ,  H01L2225/1035 ,  H01L2225/1058 ,  H01L2224/03 ,  H01L2224/83

摘要： In a manufacturing method for layered chip packages, a layered substructure with at least one additional package joined thereto is used to produce a plurality of layered chip packages. The layered substructure includes a plurality of main bodies to be separated from each other later. Each main body includes: a main part having top and bottom surfaces and including a plurality of layer portions stacked on each other; and a plurality of main terminals disposed on at least one of the top and bottom surfaces of the main part. The additional package includes an additional semiconductor chip and at least one additional terminal that is electrically connected to the additional semiconductor chip and in contact with at least one of the plurality of main terminals.

摘要翻译： 在层叠芯片封装的制造方法中，使用具有与其连接的至少一个附加封装的分层子结构来制造多个分层芯片封装。 分层子结构包括稍后要彼此分离的多个主体。 每个主体包括：具有顶表面和底表面并且包括彼此堆叠的多个层部分的主要部分; 以及设置在主要部件的顶表面和底表面中的至少一个上的多个主端子。 附加封装包括附加的半导体芯片和至少一个额外的端子，其电连接到附加的半导体芯片并与多个主端子中的至少一个接触。

公开(公告)号：US08867169B2

公开(公告)日：2014-10-21

申请号：US13473159

申请日：2012-05-16

申请人： Yoshitaka Sasaki ,  Hiroyuki Ito ,  Shigeki Tanemura ,  Kazuki Sato ,  Yukinori Ikegawa ,  Atsushi Iijima ,  Tatsuya Shimizu

发明人： Yoshitaka Sasaki ,  Hiroyuki Ito ,  Shigeki Tanemura ,  Kazuki Sato ,  Yukinori Ikegawa ,  Atsushi Iijima ,  Tatsuya Shimizu

IPC分类号： G11B5/127 ,  G11B5/147

CPC分类号： G11B5/3116 ,  G11B5/1278 ,  G11B5/3123 ,  G11B5/315 ,  G11B5/3163

摘要： A magnetic head includes a magnetic structure incorporating a write shield. The magnetic structure is formed to include a first magnetic layer, a second magnetic layer stacked on the first magnetic layer, and a seed layer. The first magnetic layer has a front end face located in the medium facing surface and a top surface. The second magnetic layer has a front end face located in the medium facing surface and a bottom surface. The top surface of the first magnetic layer includes a first region including an end located in the medium facing surface and a second region farther from the medium facing surface than the first region. The seed layer is not present on the first region of the top surface of the first magnetic layer but is present on the second region.

摘要翻译： 磁头包括结合有写入屏蔽的磁性结构。 磁结构形成为包括第一磁性层，堆叠在第一磁性层上的第二磁性层和种子层。 第一磁性层具有位于介质相对表面中的前端面和顶面。 第二磁性层具有位于介质面向表面中的前端面和底面。 第一磁性层的顶表面包括第一区域和第二区域，第一区域包括位于介质面向表面中的端部以及比介质面向表面比第一区域更远的第二区域。 种子层不存在于第一磁性层的顶表面的第一区域上，但存在于第二区域上。

公开(公告)号：US08576514B2

公开(公告)日：2013-11-05

申请号：US13328431

申请日：2011-12-16

申请人： Yoshitaka Sasaki ,  Hiroyuki Ito ,  Shigeki Tanemura ,  Kazuki Sato ,  Atsushi Iijima

发明人： Yoshitaka Sasaki ,  Hiroyuki Ito ,  Shigeki Tanemura ,  Kazuki Sato ,  Atsushi Iijima

IPC分类号： G11B5/127

CPC分类号： G11B5/1278 ,  G11B5/3116 ,  G11B5/3123 ,  G11B5/3133 ,  G11B5/3136 ,  G11B5/315 ,  G11B5/607

摘要： A thin-film magnetic head is constructed such that a main magnetic pole layer, a write shield layer, a gap layer, and a thin-film coil are laminated on a substrate. The thin-film magnetic head has a shield magnetic layer. The shield magnetic layer has a leading shield part. The leading shield part is disposed on a substrate side of the main magnetic pole layer. The leading shield part has a variable distance structure in which a rearmost part most distanced from the medium-opposing surface is distanced more from the main magnetic pole layer than is a foremost part on the main magnetic pole layer side.

摘要翻译： 薄膜磁头被构造为使得主磁极层，写入屏蔽层，间隙层和薄膜线圈层叠在基板上。 薄膜磁头具有屏蔽磁性层。 屏蔽磁性层具有前导屏蔽部分。 前导屏蔽部分设置在主磁极层的基板侧。 前导屏蔽部分具有可变的距离结构，其中最远离介质相对表面的最远部分比主磁极层侧的最前部更远离主磁极层。

公开(公告)号：US08552534B2

公开(公告)日：2013-10-08

申请号：US13286728

申请日：2011-11-01

申请人： Yoshitaka Sasaki ,  Hiroyuki Ito ,  Shigeki Tanemura ,  Kazuki Sato ,  Atsushi Iijima

发明人： Yoshitaka Sasaki ,  Hiroyuki Ito ,  Shigeki Tanemura ,  Kazuki Sato ,  Atsushi Iijima

IPC分类号： H01L23/544 ,  H01L23/34

CPC分类号： H01L25/0657 ,  H01L22/32 ,  H01L24/05 ,  H01L24/24 ,  H01L24/25 ,  H01L24/82 ,  H01L24/83 ,  H01L24/92 ,  H01L24/94 ,  H01L24/96 ,  H01L25/50 ,  H01L2224/02375 ,  H01L2224/02379 ,  H01L2224/04105 ,  H01L2224/05548 ,  H01L2224/05551 ,  H01L2224/05554 ,  H01L2224/05644 ,  H01L2224/05647 ,  H01L2224/06135 ,  H01L2224/24011 ,  H01L2224/24105 ,  H01L2224/24146 ,  H01L2224/244 ,  H01L2224/245 ,  H01L2224/25175 ,  H01L2224/2919 ,  H01L2224/32145 ,  H01L2224/82039 ,  H01L2224/82101 ,  H01L2224/83005 ,  H01L2224/83191 ,  H01L2224/9202 ,  H01L2224/92244 ,  H01L2224/94 ,  H01L2224/96 ,  H01L2225/06524 ,  H01L2225/06548 ,  H01L2225/06565 ,  H01L2924/07802 ,  H01L2924/12042 ,  H01L2224/03 ,  H01L2924/00014 ,  H01L2924/00012 ,  H01L2924/01029 ,  H01L2224/83 ,  H01L2224/82 ,  H01L2924/00

摘要： In a laminated semiconductor substrate, a plurality of semiconductor substrates are laminated. Each of the semiconductor substrate has a plurality of scribe-groove parts formed along scribe lines. Further, each of the semiconductor substrate has a plurality of device regions having a semiconductor device formed therein and insulated from each other, and a plurality of wiring electrodes connected to the semiconductor devices respectively formed in the plurality of device regions and extending from the device regions into the inside of the scribe-groove parts. The plurality of wiring electrodes are arranged in a partial arrangement pattern in which the wiring electrodes are arranged along only a part of four boundary sides, corresponding to boundaries between each of the device regions and the scribe-groove parts. Further, the plurality of wiring electrodes extend into the scribe-groove part from only one of two device regions adjacent to each other with the scribe-groove part therebetween.

摘要翻译： 在层叠半导体衬底中层叠多个半导体衬底。 每个半导体衬底具有沿着划线形成的多个划线槽部分。 此外，每个半导体衬底具有多个器件区域，其中形成有彼此绝缘的半导体器件，以及多个布线电极，其连接到分别形成在多个器件区域中并从器件区域延伸的半导体器件 进入划痕槽部分的内部。 多个布线电极以局部布置图案布置，其中布线电极仅沿着四个边界侧的一部分布置，对应于每个装置区域和划线槽部分之间的边界。 此外，多个布线电极仅从彼此相邻的两个器件区域中的一个延伸到划线槽部分中，其间具有划线槽部分。

公开(公告)号：US08466562B2

公开(公告)日：2013-06-18

申请号：US12585778

申请日：2009-09-24

申请人： Yoshitaka Sasaki ,  Hiroyuki Ito ,  Hiroshi Ikejima ,  Atsushi Iijima

发明人： Yoshitaka Sasaki ,  Hiroyuki Ito ,  Hiroshi Ikejima ,  Atsushi Iijima

IPC分类号： H01L23/48

CPC分类号： H01L24/94 ,  H01L23/481 ,  H01L24/11 ,  H01L25/0657 ,  H01L25/50 ,  H01L2224/0401 ,  H01L2224/05554 ,  H01L2224/0557 ,  H01L2224/1147 ,  H01L2224/13099 ,  H01L2225/06513 ,  H01L2225/06541 ,  H01L2225/06596 ,  H01L2924/0002 ,  H01L2924/01005 ,  H01L2924/01006 ,  H01L2924/01033 ,  H01L2924/01078 ,  H01L2924/01082 ,  H01L2924/014 ,  H01L2924/3025 ,  H01L2224/05552

摘要： A layered chip package includes a plurality of layer portions that are stacked, each of the layer portions including a semiconductor chip. The plurality of layer portions include at least one first-type layer portion and at least one second-type layer portion. The semiconductor chip has a circuit, a plurality of electrode pads electrically connected to the circuit, and a plurality of through electrodes. In every vertically adjacent two of the layer portions, the plurality of through electrodes of the semiconductor chip of one of the two layer portions are electrically connected to the respective corresponding through electrodes of the semiconductor chip of the other of the two layer portions. The first-type layer portion includes a plurality of wires for electrically connecting the plurality of through electrodes to the respective corresponding electrode pads, whereas the second-type layer portion does not include the wires.

摘要翻译： 分层芯片封装包括堆叠的多个层部分，每个层部分包括半导体芯片。 多个层部分包括至少一个第一类型层部分和至少一个第二类型的部分。 半导体芯片具有电路，电连接到电路的多个电极焊盘以及多个贯通电极。 在每个垂直相邻的两个层部分中，两个层部分中的一个的半导体芯片的多个通孔电连接到两个层部分中另一个的半导体芯片的相应的贯通电极。 第一型层部分包括用于将多个贯通电极电连接到各个对应的电极焊盘的多条导线，而第二型层部分不包括导线。