公开(公告)号：US20100091163A1

公开(公告)日：2010-04-15

申请号：US12557154

申请日：2009-09-10

申请人： Yin-Kai Liao ,  Han-Chi Liu ,  Yuan-Hung Liu ,  Dun-Nian Yaung ,  Jen-Cheng Liu

发明人： Yin-Kai Liao ,  Han-Chi Liu ,  Yuan-Hung Liu ,  Dun-Nian Yaung ,  Jen-Cheng Liu

IPC分类号： H04N5/335 ,  H01L31/0232

CPC分类号： H01L27/14629 ,  H01L21/76829 ,  H01L21/76831 ,  H01L27/14603 ,  H01L27/14614 ,  H01L27/14621 ,  H01L27/14627 ,  H01L27/1463 ,  H01L27/14636 ,  H01L27/1464 ,  H01L27/14645 ,  H01L27/14683 ,  H01L27/14685 ,  H04N3/155

摘要： A system and method for image sensing is disclosed. An embodiment comprises a substrate with a pixel region and a logic region. A first resist protect oxide (RPO) is formed over the pixel region, but not over the logic region. Silicide contacts are formed on the top of active devices formed in the pixel region, but not on the surface of the substrate in the pixel region, and silicide contacts are formed both on the top of active devices and on the surface of the substrate in the logic region. A second RPO is formed over the pixel region and the logic region, and a contact etch stop layer is formed over the second RPO. These layers help to reflect light back to the image sensor when light impinges the sensor from the backside of the substrate, and also helps prevent damage that occurs from overetching.

摘要翻译： 公开了一种用于图像感测的系统和方法。 实施例包括具有像素区域和逻辑区域的基板。 在像素区域上形成第一抗蚀保护氧化物（RPO），但不在逻辑区域上。 硅化物接触形成在像素区域中形成的有源器件的顶部上，而不是在像素区域中的衬底的表面上，并且在有源器件的顶部和衬底的表面上形成硅化物接触 逻辑区域。 在像素区域和逻辑区域上形成第二RPO，并且在第二RPO上形成接触蚀刻停止层。 当光从基板的背面入射传感器时，这些层有助于将光反射回图像传感器，并且还有助于防止由过蚀刻引起的损坏。

公开(公告)号：US20060192083A1

公开(公告)日：2006-08-31

申请号：US10906604

申请日：2005-02-25

申请人： Shih-Chi Fu ,  Yuan-Hung Liu ,  Kuo-Yin Lin ,  Feng-Jia Shiu ,  Chia-Shiung Tsai ,  Ching-Sen Kuo ,  Jieh-Jang Chen

发明人： Shih-Chi Fu ,  Yuan-Hung Liu ,  Kuo-Yin Lin ,  Feng-Jia Shiu ,  Chia-Shiung Tsai ,  Ching-Sen Kuo ,  Jieh-Jang Chen

IPC分类号： H01L27/00 ,  H01L31/00

CPC分类号： H01L27/14685 ,  H01L27/1462 ,  H01L27/14625 ,  H01L27/14654

摘要： Described is a light-directing feature formed in the inter-level dielectric (ILD) layer in combination with an anti-reflective (AR) layer to effectively and simultaneously increase quantum efficiency and cross-talk immunity thereby improving photonic performances of photo-sensitive integrated circuits. A plurality of photosensor cells is formed on a semiconductor substrate. An AR layer is subsequently formed on the plurality of photosensor cells, the AR layer being substantially non-reflective of incident light. An ILD layer is then formed over the AR layer, the ILD layer comprising a plurality of light-directing features formed in openings in the ILD layer over the AR layer above and about certain of the plurality of photosensor cells.

摘要翻译： 描述了在层间电介质（ILD）层中形成的与抗反射（AR）层组合的光导特征，以有效并同时地提高量子效率和串扰抗扰度，从而改善光敏集成的光子性能 电路。 多个光电传感器单元形成在半导体基板上。 随后在多个光电传感器单元上​​形成AR层，AR层基本上不反射入射光。 然后在AR层上形成ILD层，ILD层包括多个导光特征，其形成在ILD层中的多个光敏元件上方和周围的AR层上的开口中。

公开(公告)号：US06291312B1

公开(公告)日：2001-09-18

申请号：US09395108

申请日：1999-09-14

申请人： Bor-Wen Chan ,  Yuan-Hung Liu

发明人： Bor-Wen Chan ,  Yuan-Hung Liu

IPC分类号： H01L2176

CPC分类号： H01L21/76224

摘要： A method for forming a pullback opening above a shallow trench isolation structure. A patterned mask layer is formed over a substrate. A sacrificial layer is formed on the sidewalls of the mask layer. The exposed portion of the substrate is etched to form a trench in the substrate. The sacrificial layer is removed to increase the width of the opening above the trench.

摘要翻译： 一种用于在浅沟槽隔离结构上形成回拉开口的方法。 在衬底上形成图案化掩模层。 牺牲层形成在掩模层的侧壁上。 蚀刻衬底的暴露部分以在衬底中形成沟槽。 去除牺牲层以增加沟槽上方的开口的宽度。

公开(公告)号：US06232175B1

公开(公告)日：2001-05-15

申请号：US09466044

申请日：1999-12-17

申请人： Yuan-Hung Liu ,  Bor-Wen Chan

发明人： Yuan-Hung Liu ,  Bor-Wen Chan

IPC分类号： H01L218242

CPC分类号： H01L28/92 ,  H01L21/32139 ,  H01L27/10852

摘要： A double recess crown-shaped DRAM capacitor is formed in a simplified process. A dielectric layer is formed over a substrate. Using photolithographic and etching techniques, a contact opening is formed in the dielectric layer. A conductive layer is formed over the dielectric layer filling the contact opening to form a conductive plug. A second dielectric layer is formed over the conductive layer. Again using photolithographic and etching techniques, the second dielectric layer is patterned to form a trapezoidal-shaped dielectric layer. An organic bottom anti-reflective coating (organic BARC) is coated over the trapezoidal-shaped dielectric layer and the conductive layer. Organic BARC above the trapezoidal-shaped dielectric layer is removed. Using the organic BARC as an etching mask, the trapezoidal-shaped dielectric layer is etched to form triangular-shaped dielectric layers and a trench in the conductive layer. The residual organic BARC is completely removed. Using the triangular-shaped dielectric layers as a hard etching mask, two types of trenches each having a different depth are formed in the conductive layer. The triangular-shaped dielectric layers are removed to form a double-recess lower electrode. Hemispherical silicon grains are grown over the interior surface of the double-recess lower electrode as well as the external sidewalls. Finally, a conformal dielectric layer and a conformal conductive layer are sequentially formed over the surface of the double-recess lower electrode.

摘要翻译： 以简化的工艺形成双凹槽冠状DRAM电容器。 介电层形成在衬底上。 使用光刻和蚀刻技术，在电介质层中形成接触开口。 在填充接触开口的电介质层上形成导电层以形成导电插塞。 在导电层上形成第二介电层。 再次使用光刻和蚀刻技术，将第二介电层图案化以形成梯形介电层。 将有机底部抗反射涂层（有机BARC）涂覆在梯形介电层和导电层上。 去除梯形介电层上方的有机BARC。 使用有机BARC作为蚀刻掩模，蚀刻梯形介电层以在导电层中形成三角形介电层和沟槽。 残留的有机BARC被完全去除。 使用三角形介电层作为硬蚀刻掩模，在导电层中形成各具有不同深度的两种类型的沟槽。 去除三角形电介质层以形成双凹槽下电极。 半球状硅晶粒生长在双凹槽下电极的内表面以及外侧壁上。 最后，在双凹槽下电极的表面上依次形成保形电介质层和保形导电层。

公开(公告)号：US20140061924A1

公开(公告)日：2014-03-06

申请号：US13601265

申请日：2012-08-31

申请人： Hsin-Yu Chen ,  Ku-Feng Yang ,  Tasi-Jung Wu ,  Lin-Chih Huang ,  Yuan-Hung Liu ,  Tsang-Jiuh Wu ,  Wen-Chih Chiou

发明人： Hsin-Yu Chen ,  Ku-Feng Yang ,  Tasi-Jung Wu ,  Lin-Chih Huang ,  Yuan-Hung Liu ,  Tsang-Jiuh Wu ,  Wen-Chih Chiou

IPC分类号： H01L23/522 ,  H01L21/768

CPC分类号： H01L23/528 ,  H01L21/76807 ,  H01L23/3114 ,  H01L23/3171 ,  H01L23/481 ,  H01L23/5226 ,  H01L23/53223 ,  H01L23/53238 ,  H01L23/53266 ,  H01L23/5384 ,  H01L27/0617 ,  H01L2221/1031 ,  H01L2224/13 ,  H01L2924/13091 ,  H01L2924/00

摘要： An apparatus comprises an interlayer dielectric layer formed on a first side of a substrate, a first metallization layer formed over the interlayer dielectric layer, wherein the first metallization layer comprises a first metal line and a dielectric layer formed over the first metallization layer, wherein the dielectric layer comprises a metal structure having a bottom surface coplanr with a top surface of the first metal line.

摘要翻译： 一种装置包括形成在衬底的第一侧上的层间绝缘层，形成在层间介电层上的第一金属化层，其中第一金属化层包括形成在第一金属化层上的第一金属线和介电层，其中， 电介质层包括具有与第一金属线的顶表面共面的底表面的金属结构。

公开(公告)号：US20090124073A1

公开(公告)日：2009-05-14

申请号：US12354171

申请日：2009-01-15

申请人： Ming-Chyi Liu ,  Yuan-Hung Liu ,  Gwo-Yuh Shiau ,  Yuan-Chih Hsieh ,  Chi-Hsin Lo ,  Chia-Shiung Tsai

发明人： Ming-Chyi Liu ,  Yuan-Hung Liu ,  Gwo-Yuh Shiau ,  Yuan-Chih Hsieh ,  Chi-Hsin Lo ,  Chia-Shiung Tsai

IPC分类号： H01L21/768

CPC分类号： H01L24/05 ,  H01L24/45 ,  H01L24/48 ,  H01L27/14636 ,  H01L27/14643 ,  H01L2224/02166 ,  H01L2224/04042 ,  H01L2224/05093 ,  H01L2224/05096 ,  H01L2224/05556 ,  H01L2224/05558 ,  H01L2224/05624 ,  H01L2224/45144 ,  H01L2224/45147 ,  H01L2224/45155 ,  H01L2224/45166 ,  H01L2224/4807 ,  H01L2224/4845 ,  H01L2224/48463 ,  H01L2224/48505 ,  H01L2224/48624 ,  H01L2224/48824 ,  H01L2924/01005 ,  H01L2924/01007 ,  H01L2924/01013 ,  H01L2924/01014 ,  H01L2924/01015 ,  H01L2924/01019 ,  H01L2924/01022 ,  H01L2924/01027 ,  H01L2924/01028 ,  H01L2924/01029 ,  H01L2924/01032 ,  H01L2924/01033 ,  H01L2924/01072 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/01082 ,  H01L2924/01327 ,  H01L2924/05042 ,  H01L2924/09701 ,  H01L2924/10253 ,  H01L2924/14 ,  H01L2924/00014 ,  H01L2224/05666 ,  H01L2224/45124 ,  H01L2224/05655 ,  H01L2924/00

摘要： A method for forming a semiconductor device with a bonding pad is disclosed. A first substrate having a device area and a bonding area is provided, wherein the first substrate has an upper surface and a bottom surface. Semiconductor elements are formed on the upper surface of the first substrate in the device area. A first inter-metal dielectric layer is formed on the upper surface of the substrate in the bonding area. A lowermost metal pattern is formed in the first inter-metal dielectric layer, wherein the lowermost metal pattern serves as the bonding pad. An opening through the first substrate is formed to expose the lowermost metal pattern.

摘要翻译： 公开了一种用焊盘形成半导体器件的方法。 提供具有器件面积和接合面积的第一衬底，其中第一衬底具有上表面和底表面。 半导体元件形成在器件区域中的第一衬底的上表面上。 在接合区域中的基板的上表面上形成第一金属间介电层。 在第一金属间介质层中形成最下面的金属图案，其中最下面的金属图形用作接合焊盘。 形成通过第一基板的开口以露出最下面的金属图案。

公开(公告)号：US20090051034A1

公开(公告)日：2009-02-26

申请号：US11892103

申请日：2007-08-20

申请人： Chih-Yang Pai ,  Yuan-Hung Liu ,  Michael Kuang ,  Kuo-Ching Huang

发明人： Chih-Yang Pai ,  Yuan-Hung Liu ,  Michael Kuang ,  Kuo-Ching Huang

IPC分类号： H01L23/52 ,  H01L21/44

CPC分类号： H01L27/10888 ,  H01L21/76844

摘要： A method for forming a semiconductor device is provided. The method includes the following steps. A substrate having a first contact is provided. A layered structure is formed on the substrate. A recess is formed into the layered structure to expose at least a portion of the first contact. A glue layer is formed on the layered structure and the at least a portion of the first contact. The glue layer is removed from the at least a portion of the first contact. A second contact is formed contacting the first contact and the glue layer.

摘要翻译： 提供一种形成半导体器件的方法。 该方法包括以下步骤。 提供具有第一触点的基板。 在基板上形成层状结构。 形成层状结构中的凹部以暴露第一接触件的至少一部分。 在层状结构和第一接触的至少一部分上形成胶层。 胶层从第一接触件的至少一部分去除。 形成接触第一接触和胶层的第二接触。

公开(公告)号：US07189957B2

公开(公告)日：2007-03-13

申请号：US10906604

申请日：2005-02-25

申请人： Shih-Chi Fu ,  Yuan-Hung Liu ,  Kuo-Yin Lin ,  Feng-Jia Shiu ,  Chia-Shiung Tsai ,  Ching-Sen Kuo ,  Jieh-Jang Chen

发明人： Shih-Chi Fu ,  Yuan-Hung Liu ,  Kuo-Yin Lin ,  Feng-Jia Shiu ,  Chia-Shiung Tsai ,  Ching-Sen Kuo ,  Jieh-Jang Chen

IPC分类号： H01L31/00 ,  H01L21/00

CPC分类号： H01L27/14685 ,  H01L27/1462 ,  H01L27/14625 ,  H01L27/14654

摘要： Described is a light-directing feature formed in the inter-level dielectric (ILD) layer in combination with an anti-reflective (AR) layer to effectively and simultaneously increase quantum efficiency and cross-talk immunity thereby improving photonic performances of photo-sensitive integrated circuits. A plurality of photosensor cells is formed on a semiconductor substrate. An AR layer is subsequently formed on the plurality of photosensor cells, the AR layer being substantially non-reflective of incident light. An ILD layer is then formed over the AR layer, the ILD layer comprising a plurality of light-directing features formed in openings in the ILD layer over the AR layer above and about certain of the plurality of photosensor cells.

摘要翻译： 描述了在层间电介质（ILD）层中形成的与抗反射（AR）层组合的光导特征，以有效并同时地提高量子效率和串扰抗扰度，从而改善光敏集成的光子性能 电路。 多个光电传感器单元形成在半导体基板上。 随后在多个光电传感器单元上​​形成AR层，AR层基本上不反射入射光。 然后在AR层上形成ILD层，ILD层包括多个导光特征，其形成在ILD层中的多个光敏元件上方和周围的AR层上的开口中。

公开(公告)号：US08546235B2

公开(公告)日：2013-10-01

申请号：US13101788

申请日：2011-05-05

申请人： Sung-Hui Huang ,  Yuan-Hung Liu ,  Ming-Fa Chen

发明人： Sung-Hui Huang ,  Yuan-Hung Liu ,  Ming-Fa Chen

IPC分类号： H01L21/20

CPC分类号： H01L28/40

摘要： An integrated circuit includes a substrate and a first metal-insulator-metal (MIM) capacitor disposed over the substrate. The MIM capacitor includes a first metallic capacitor plate disposed over the substrate. At least one first insulator layer is disposed over the first metallic capacitor plate. A second metallic capacitor plate is disposed over the at least one first insulator layer. At least one first dielectric layer is disposed over the substrate. At least a portion of the at least one first dielectric layer is disposed between the first metallic capacitor plate and the at least one first insulator layer.

摘要翻译： 集成电路包括衬底和设置在衬底上的第一金属 - 绝缘体 - 金属（MIM）电容器。 MIM电容器包括设置在基板上的第一金属电容器板。 至少一个第一绝缘体层设置在第一金属电容器板上。 第二金属电容器板设置在至少一个第一绝缘体层上。 至少一个第一电介质层设置在衬底上。 所述至少一个第一介电层的至少一部分设置在所述第一金属电容器板和所述至少一个第一绝缘体层之间。

公开(公告)号：US20110081766A1

公开(公告)日：2011-04-07

申请号：US12572833

申请日：2009-10-02

申请人： Han-Chi Liu ,  Dun-Nian Yaung ,  Jen-Cheng Liu ,  Yuan-Hung Liu

发明人： Han-Chi Liu ,  Dun-Nian Yaung ,  Jen-Cheng Liu ,  Yuan-Hung Liu

IPC分类号： H01L21/762

CPC分类号： H01L27/14683 ,  H01L21/2652 ,  H01L21/266 ,  H01L21/76232 ,  H01L27/14627 ,  H01L27/1463

摘要： A method includes forming a protective layer with an opening over a substrate, thereafter implanting a dopant into a substrate region through the opening, the protective layer protecting a different substrate region, and reducing thickness of the protective layer. A different aspect includes etching a substrate to form a recess therein, thereafter implanting a dopant into a substrate region within the recess and through an opening in a protective layer provided over the substrate, and reducing thickness of the protective layer. Another aspect includes forming a protective layer over a substrate, forming photoresist having an opening over the protective layer, etching the protective layer through the opening to expose the substrate, etching the substrate to form a recess in the substrate, implanting a dopant into a substrate portion, the protective layer protecting a different substrate portion thereunder, and etching the protective layer to reduce its thickness.

摘要翻译： 一种方法包括在衬底上形成具有开口的保护层，然后通过开口将掺杂剂注入到衬底区域中，保护层保护不同的衬底区域，并减小保护层的厚度。 不同的方面包括蚀刻衬底以在其中形成凹陷，然后将掺杂剂注入到凹陷内的衬底区域中，并通过设置在衬底上的保护层中的开口，并且减小保护层的厚度。 另一方面包括在衬底上形成保护层，在保护层上形成具有开口的光致抗蚀剂，通过开口蚀刻保护层以暴露衬底，蚀刻衬底以在衬底中形成凹陷，将掺杂剂注入到衬底中 保护层保护其下的不同基板部分，并蚀刻保护层以减小其厚度。