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14 条记录 (耗时 0.024 秒)

    Semiconductor device and method for the same
    1.
    发明申请
    Semiconductor device and method for the same 审中-公开
    半导体装置及其方法相同

    公开(公告)号：US20090051034A1

    公开(公告)日：2009-02-26

    申请号：US11892103

    申请日：2007-08-20

    申请人： Chih-Yang Pai ,  Yuan-Hung Liu ,  Michael Kuang ,  Kuo-Ching Huang

    发明人： Chih-Yang Pai ,  Yuan-Hung Liu ,  Michael Kuang ,  Kuo-Ching Huang

    IPC分类号： H01L23/52 ,  H01L21/44

    CPC分类号： H01L27/10888 ,  H01L21/76844

    摘要： A method for forming a semiconductor device is provided. The method includes the following steps. A substrate having a first contact is provided. A layered structure is formed on the substrate. A recess is formed into the layered structure to expose at least a portion of the first contact. A glue layer is formed on the layered structure and the at least a portion of the first contact. The glue layer is removed from the at least a portion of the first contact. A second contact is formed contacting the first contact and the glue layer.

    摘要翻译： 提供一种形成半导体器件的方法。 该方法包括以下步骤。 提供具有第一触点的基板。 在基板上形成层状结构。 形成层状结构中的凹部以暴露第一接触件的至少一部分。 在层状结构和第一接触的至少一部分上形成胶层。 胶层从第一接触件的至少一部分去除。 形成接触第一接触和胶层的第二接触。

    Method of forming an embedded memory device
    2.
    发明授权
    Method of forming an embedded memory device 有权
    形成嵌入式存储器件的方法

    公开(公告)号：US09082705B2

    公开(公告)日：2015-07-14

    申请号：US13566710

    申请日：2012-08-03

    申请人： Yu-Wei Ting ,  Kuo-Ching Huang ,  Chih-Yang Pai

    发明人： Yu-Wei Ting ,  Kuo-Ching Huang ,  Chih-Yang Pai

    IPC分类号： H01L21/336 ,  H01L21/4763 ,  H01L21/31 ,  H01L21/28 ,  H01L29/423 ,  H01L29/66 ,  H01L29/792

    CPC分类号： H01L27/11521 ,  H01L21/28282 ,  H01L29/42324 ,  H01L29/42344 ,  H01L29/42356 ,  H01L29/66833 ,  H01L29/792

    摘要： The present disclosure describes a method of forming a memory device. The method includes receiving a wafer substrate, forming a poly stack pattern on the wafer substrate, performing an ion implantation process to form a source and a drain in the wafer substrate, forming a memory gate and a control gate in the defined poly stack pattern, and forming a control gate in the control poly stack pattern. Forming the memory gate further includes performing a memory gate recess to bury the memory gate in an oxide layer.

    摘要翻译： 本公开描述了形成存储器件的方法。 该方法包括接收晶片衬底，在晶片衬底上形成多晶堆叠图案，执行离子注入工艺以在晶片衬底中形成源极和漏极，在限定的多晶堆叠图案中形成存储栅极和控制栅极， 以及在所述控制多晶堆叠图案中形成控制栅极。 形成存储器栅极还包括执行存储器栅极凹槽以将存储栅极埋入氧化物层中。

    Method of forming contact plugs for eliminating tungsten seam issue
    3.
    发明申请
    Method of forming contact plugs for eliminating tungsten seam issue 审中-公开
    形成用于消除钨焊缝问题的接触塞的方法

    公开(公告)号：US20080217775A1

    公开(公告)日：2008-09-11

    申请号：US11714770

    申请日：2007-03-07

    申请人： Chih-Yang Pai ,  Wen-Chuan Chiang ,  Chung-Yi Yu ,  Yeur-Luen Tu ,  Yuan-Hung Liu ,  Hsiang-Fan Lee ,  Chuan-Jong Wang

    发明人： Chih-Yang Pai ,  Wen-Chuan Chiang ,  Chung-Yi Yu ,  Yeur-Luen Tu ,  Yuan-Hung Liu ,  Hsiang-Fan Lee ,  Chuan-Jong Wang

    IPC分类号： H01L23/52 ,  H01L21/4763

    CPC分类号： H01L21/76877 ,  H01L21/76849 ,  H01L27/10855 ,  H01L27/10888

    摘要： A method of forming a contact plug of an eDRAM device includes the following steps: forming a tungsten layer with tungsten seam on a dielectric layer to fill a contact hole; removing the tungsten layer from the top surface of the dielectric layer, recessing the tungsten layer in the contact hole to form a recess of about 600˜900 Angstroms in depth below the top surface of the dielectric layer, depositing a conductive layer on the dielectric layer and the recessed tungsten plug to fill the recess; and removing the conductive layer from the top surface of the dielectric layer to form a conductive plug on the recessed tungsten plug in the contact hole.

    摘要翻译： 形成eDRAM器件的接触插塞的方法包括以下步骤：在电介质层上形成具有钨接缝的钨层以填充接触孔; 从电介质层的顶表面去除钨层，使接触孔中的钨层凹陷，以在电介质层的顶表面下方深度形成约600〜900埃的凹陷，在电介质层上沉积导电层 和凹入的钨塞填充凹槽; 并且从电介质层的顶表面去除导电层，以在接触孔中的凹入的钨插塞上形成导电插塞。

    Method of Forming an Embedded Memory Device
    4.
    发明申请
    Method of Forming an Embedded Memory Device 有权
    形成嵌入式存储器件的方法

    公开(公告)号：US20140035020A1

    公开(公告)日：2014-02-06

    申请号：US13566710

    申请日：2012-08-03

    申请人： Yu-Wei Ting ,  Kuo-Ching Huang ,  Chih-Yang Pai

    发明人： Yu-Wei Ting ,  Kuo-Ching Huang ,  Chih-Yang Pai

    IPC分类号： H01L29/788 ,  H01L21/336

    CPC分类号： H01L27/11521 ,  H01L21/28282 ,  H01L29/42324 ,  H01L29/42344 ,  H01L29/42356 ,  H01L29/66833 ,  H01L29/792

    摘要： The present disclosure describes a method of forming a memory device. The method includes receiving a wafer substrate, forming a poly stack pattern on the wafer substrate, performing an ion implantation process to form a source and a drain in the wafer substrate, forming a memory gate and a control gate in the defined poly stack pattern, and forming a control gate in the control poly stack pattern. Forming the memory gate further includes performing a memory gate recess to bury the memory gate in an oxide layer.

    摘要翻译： 本公开描述了形成存储器件的方法。 该方法包括接收晶片衬底，在晶片衬底上形成多晶堆叠图案，执行离子注入工艺以在晶片衬底中形成源极和漏极，在限定的多晶堆叠图案中形成存储栅极和控制栅极， 以及在所述控制多晶堆叠图案中形成控制栅极。 形成存储器栅极还包括执行存储器栅极凹槽以将存储栅极埋入氧化物层中。

    Integrating a DRAM with an SRAM having butted contacts and resulting devices
    5.
    发明申请
    Integrating a DRAM with an SRAM having butted contacts and resulting devices 审中-公开
    将DRAM与具有对接触点和所产生的器件的SRAM集成

    公开(公告)号：US20080116496A1

    公开(公告)日：2008-05-22

    申请号：US11809642

    申请日：2007-06-01

    申请人： Kuo-Chyuan Tzeng ,  Kuo-Chiang Ting ,  Chen-Jong Wang ,  Min-Hsiung Chiang ,  Chih-Yang Pai

    发明人： Kuo-Chyuan Tzeng ,  Kuo-Chiang Ting ,  Chen-Jong Wang ,  Min-Hsiung Chiang ,  Chih-Yang Pai

    IPC分类号： H01L27/108

    CPC分类号： H01L27/105 ,  H01L27/10894 ,  H01L27/11 ,  H01L27/1116

    摘要： A novel SOC structure and method of making the same are provided. An SOC comprises a logic region, an SRRM and a DRAM region. The storage capacitor in a DRAM cell is formed in the first dielectric layer in an MIM (metal-insulator-metal) configuration, having a large vertical surface area. A butted contact, formed in said first dielectric layer, comprises a bottom portion abutting a first and second conductive region in an SRAM cell, and a vertically aligned top portion coupled to a first metal layer. The top portion has a substantially larger depth than that of the bottom portion, while substantially smaller in size. Forming this SOC structure does not require adding complex, error-prone additional processing steps on an existing CMOS manufacturing process, thus having little impact on the overall SOC product yield.

    摘要翻译： 提供了一种新颖的SOC结构及其制造方法。 SOC包括逻辑区域，SRRM和DRAM区域。 金属 - 绝缘体 - 金属）构造中的DRAM单元中的存储电容器形成在第一介电层中，具有大的垂直表面积。 形成在所述第一电介质层中的对接触点包括邻接SRAM单元中的第一和第二导电区域的底部以及耦合到第一金属层的垂直对齐的顶部。 顶部具有比底部大的深度大得多的深度，而其尺寸基本上更小。 形成这种SOC结构不需要在现有的CMOS制造工艺上增加复杂的，容易出错的附加处理步骤，因此对整个SOC产品产量几乎没有影响。

    Method of forming shallow trench isolation with rounded corner and divot-free by using disposable spacer
    7.
    发明授权
    Method of forming shallow trench isolation with rounded corner and divot-free by using disposable spacer 有权
    通过使用一次性间隔件形成具有圆角和无凹槽的浅沟槽隔离的方法

    公开(公告)号：US06555442B1

    公开(公告)日：2003-04-29

    申请号：US10042075

    申请日：2002-01-08

    申请人： Chih-Yang Pai ,  Chih-Hsing Yu ,  Yeur-Luen Tu ,  Chia-Shiung Tsai ,  Min-Hwa Chi

    发明人： Chih-Yang Pai ,  Chih-Hsing Yu ,  Yeur-Luen Tu ,  Chia-Shiung Tsai ,  Min-Hwa Chi

    IPC分类号： H01L2176

    CPC分类号： H01L21/76235

    摘要： A method of fabricating an STI, comprising the following steps. A silicon structure having a pad oxide layer formed thereover is provided. An undoped poly buffer layer is formed over the pad oxide layer. A hard mask layer is formed over the undoped poly buffer layer. The hard mask layer, the undoped poly buffer layer and the pad oxide layer are patterned to form an opening exposing a portion of the silicon structure within an active area. The opening having exposed side walls. Inorganic spacers are formed over the exposed side walls. Using the patterned hard mask layer and the spacers as hard masks, the silicon structure is etched to form an STI opening within the active area. The inorganic spacers are removed exposing the upper corners of the STI opening. Using an oxidation process, a liner oxide layer is formed within the STI opening, over the upper corners of the STI opening and at least the patterned undoped poly buffer layer exposed by the removal of the inorganic spacers. An STI oxide layer is formed over the patterned hard mask layer, filling the liner oxide layer lined STI opening. The STI oxide layer is planarized and the patterned hard mask, the patterned undoped poly buffer layer and the patterned pad oxide layer are removed to fabricate the STI having rounded corners and without substantial divots.

    摘要翻译： 一种制造STI的方法，包括以下步骤。 提供了具有形成在其上的衬垫氧化物层的硅结构。 在衬垫氧化物层上形成未掺杂的多晶缓冲层。 在未掺杂的多缓冲层上形成硬掩模层。 将硬掩模层，未掺杂的多晶缓冲层和焊盘氧化物层图案化以形成暴露有源区域内的硅结构的一部分的开口。 开口具有暴露的侧壁。 在暴露的侧壁上形成无机间隔物。 使用图案化的硬掩模层和间隔物作为硬掩模，蚀刻硅结构以在有效区域内形成STI开口。 去除暴露STI开口的上角的无机间隔物。 使用氧化工艺，在STI开口内，在STI开口的上角上形成衬里氧化物层，并且至少通过去除无机间隔物露出图案化的未掺杂多缓冲层。 在图案化的硬掩模层之上形成STI氧化物层，填充衬里氧化物层衬里的STI开口。 将STI氧化物层平坦化，并且去除图案化的硬掩模，图案化的未掺杂多缓冲层和图案化的衬垫氧化物层，以制造具有圆角并且没有实质上的纹理的STI。