公开(公告)号：US20110161568A1

公开(公告)日：2011-06-30

申请号：US12876247

申请日：2010-09-07

Applicant: Ricardo H. Bruce ,  Elsbeth Lauren Tagayo Villapana ,  Joel Alonzo Baylon

Inventor： Ricardo H. Bruce ,  Elsbeth Lauren Tagayo Villapana ,  Joel Alonzo Baylon

IPC: G06F12/00 ,  G06F13/36

CPC classification number: G06F13/1657 ,  G06F12/00 ,  G06F12/0246 ,  G06F13/1673 ,  G06F13/1684 ,  G06F13/36

Abstract: The present invention relates to a multilevel memory bus system for transferring information between at least one DMA controller and at least one solid-state semiconductor memory device, such as NAND flash memory devices or the like. This multilevel memory bus system includes at least one DMA controller coupled to an intermediate bus; a flash memory bus; and a flash buffer circuit between the intermediate bus and the flash memory bus. This multilevel memory bus system may be disposed to support: an n-bit wide bus width, such as nibble-wide or byte-wide bus widths; a selectable data sampling rate, such as a single or double sampling rate, on the intermediate bus; a configurable bus data rate, such as a single, double, quad, or octal data sampling rate; CRC protection; an exclusive busy mechanism; dedicated busy lines; or any combination of these.

Abstract translation: 本发明涉及用于在至少一个DMA控制器与至少一个固态半导体存储器件（诸如NAND闪存器件等）之间传送信息的多电平存储器总线系统。 该多电平存储器总线系统包括耦合到中间总线的至少一个DMA控制器; 闪存总线; 以及中间总线和闪存总线之间的闪存缓冲电路。 该多级存储器总线系统可以被设置为支持：n位宽的总线宽度，例如半字节宽度或字节宽度的总线宽度; 中间总线上的可选择的数据采样率，例如单次或双次采样率; 可配置的总线数据速率，例如单，双，四进制或八进制数据采样率; CRC保护; 独家繁忙的机制; 专线忙 或这些的任何组合。

公开(公告)号：US07826243B2

公开(公告)日：2010-11-02

申请号：US11322442

申请日：2005-12-29

Applicant: Rey Bruce ,  Ricardo Bruce ,  Patrick Digamon Bugayong ,  Joel Alonzo Baylon

Inventor： Rey Bruce ,  Ricardo Bruce ,  Patrick Digamon Bugayong ,  Joel Alonzo Baylon

IPC: G11C5/02

CPC classification number: H01L25/105 ,  H01L24/16 ,  H01L25/0655 ,  H01L25/18 ,  H01L2224/16 ,  H01L2225/1005 ,  H01L2225/1023 ,  H01L2225/1058 ,  H01L2924/01079 ,  H01L2924/15331 ,  H01L2924/1627

Abstract: Stacking techniques are illustrated in example embodiments of the present invention wherein semiconductor dies are mounted in a module to become a MCM which serves as the basic building block. A combination of these modules and dies in a substrate creates a package with specific function or a range of memory capacity. Several example system configurations are provided using BGA and PGA to illustrate the stacking technique. Several pin assignment and signal routing techniques are illustrated wherein internal and external signals are routed from main board to various stacked modules. Expansion can be done both on the vertical and horizontal orientations.

Abstract translation: 堆叠技术在本发明的示例性实施例中示出，其中将半导体管芯安装在模块中以成为用作基本构建块的MCM。 衬底中的这些模块和管芯的组合产生具有特定功能或一系列存储器容量的封装。 使用BGA和PGA提供了几个示例系统配置来说明堆叠技术。 示出了几个引脚分配和信号路由技术，其中内部和外部信号从主板路由到各种堆叠的模块。 可以在垂直和水平方向进行扩展。

公开(公告)号：US20070288686A1

公开(公告)日：2007-12-13

申请号：US11450005

申请日：2006-06-08

Applicant: Mark Arcedera ,  Reyjan Lanuza ,  Ritchie Babaylan

Inventor： Mark Arcedera ,  Reyjan Lanuza ,  Ritchie Babaylan

IPC: G06F12/00

CPC classification number: G06F12/0246

Abstract: A data storage system is provided comprising several flash arrays in a board and stacking these boards to attain a high-capacity solid state hard drive. A remap table is used to map all logical addresses from a host system to the actual physical addresses where data are stored. The assignments of these physical locations are done in such a way that the load of the system is evenly distributed to its available resources. This would ensure that the storage system will run at its utmost efficiency utilizing its resources properly. To achieve this, the system would make sure that the physical location of data be evenly distributed according to the current load of the system.

Abstract translation: 提供一种数据存储系统，其包括板中的几个闪存阵列并且堆叠这些板以获得高容量固态硬盘驱动器。 重映射表用于将来自主机系统的所有逻辑地址映射到存储数据的实际物理地址。 这些物理位置的分配以使系统的负载均匀分布到其可用资源的方式完成。 这将确保存储系统以最佳效率利用其资源正常运行。 为了实现这一点，系统将确保数据的物理位置根据系统的当前负载均匀分布。

公开(公告)号：US10423554B1

公开(公告)日：2019-09-24

申请号：US15790299

申请日：2017-10-23

Applicant: BiTMICRO Networks, Inc.

Inventor： Ricardo H. Bruce ,  Cyrill Coronel Ponce ,  Jarmie Dela Cruz Espuerta

IPC: G06F13/20 ,  G06F13/366 ,  G06F13/00

Abstract: In one embodiment of the invention, a system architecture for bus masters and bus arbiters are provided to support routing and failover. The system comprises large pools of bus masters, a plurality of sets can be configured to control a plurality of slave devices wherein each set contains a collection of bus masters attached to central arbiter driving one of the system buses. Each set controls a group(s) of slave device that are primarily controlled by the bus master(s) within the set. Hence, a system can therefore include of a plurality of sets and can control a group of slave devices.

公开(公告)号：US09934045B1

公开(公告)日：2018-04-03

申请号：US14684399

申请日：2015-04-12

Applicant: BiTMICRO Networks, Inc.

Inventor： Alvin Anonuevo Manlapat ,  Ian Victor Pasion Beleno

IPC: G06F1/12 ,  G06F9/44 ,  G06F1/24 ,  G06F12/02 ,  G11C7/10

CPC classification number: G06F9/4401 ,  G06F1/24 ,  G06F12/0246 ,  G06F2212/7201 ,  G11C7/1072 ,  G11C8/16

Abstract: In an embodiment of the invention, an apparatus comprises an embedded system comprising: a processor configured to execute firmware; a random access memory (RAM) configured to store firmware and a multi-port memory controller configured to interface with the RAM; a power-on reset (POR) sequencer configured to control a boot process of the embedded system; a nonvolatile memory configured to store data used by the POR sequencer in the boot process and a nonvolatile memory controller configured to interface with the nonvolatile memory; a direct memory access (DMA) controller configured initiate and track data transfers; and a configuration and status register (CSR) controller configured to access modules in the embedded system.

公开(公告)号：US09798688B1

公开(公告)日：2017-10-24

申请号：US14216627

申请日：2014-03-17

Applicant: BiTMICRO Networks, Inc.

Inventor： Ricardo H. Bruce ,  Cyrill Coronel Ponce ,  Jarmie Dela Cruz Espuerta

IPC: G06F13/20 ,  G06F13/366 ,  G06F13/00

CPC classification number: G06F13/366

Abstract: In one embodiment of the invention, a system architecture for bus masters and bus arbiters are provided to support routing and failover. The system comprises large pools of bus masters, a plurality of sets can be configured to control a plurality of slave devices wherein each set contains a collection of bus masters attached to central arbiter driving one of the system buses. Each set controls a group(s) of slave device that are primarily controlled by the bus master(s) within the set. Hence, a system can therefore include of a plurality of sets and can control a group of slave devices.

公开(公告)号：US09734067B1

公开(公告)日：2017-08-15

申请号：US14689045

申请日：2015-04-16

Applicant: BiTMICRO Networks, Inc.

Inventor： Rolando H. Bruce ,  Elmer Paule Dela Cruz ,  Mark Ian Alcid Arcedera

IPC: G06F12/0831 ,  G06F12/0875

CPC classification number: G06F12/0833 ,  G06F11/1076 ,  G06F12/0804 ,  G06F12/0811 ,  G06F12/0844 ,  G06F12/0868 ,  G06F12/0875 ,  G06F2212/1016 ,  G06F2212/217 ,  G06F2212/225 ,  G06F2212/313 ,  G06F2212/452 ,  G06F2212/62

Abstract: A hybrid storage system is described having a mixture of different types of storage devices comprising rotational drives, flash devices, SDRAM, and SRAM. The rotational drives are used as the main storage, providing lowest cost per unit of storage memory. Flash memory is used as a higher-level cache for rotational drives. Methods for managing multiple levels of cache for this storage system is provided having a very fast Level 1 cache which consists of volatile memory (SRAM or SDRAM), and a non-volatile Level 2 cache using an array of flash devices. It describes a method of distributing the data across the rotational drives to make caching more efficient. It also describes efficient techniques for flushing data from L1 cache and L2 cache to the rotational drives, taking advantage of concurrent flash devices operations, concurrent rotational drive operations, and maximizing sequential access types in the rotational drives rather than random accesses which are relatively slower. Methods provided here may be extended for systems that have more than two cache levels.

公开(公告)号：US09400617B2

公开(公告)日：2016-07-26

申请号：US14217467

申请日：2014-03-17

Applicant: Cyrill Ponce ,  Marizonne Operio Fuentes ,  Gianico Geonzon Noble

Inventor： Cyrill Ponce ,  Marizonne Operio Fuentes ,  Gianico Geonzon Noble

IPC: G06F3/00 ,  G06F3/06 ,  G06F12/08

CPC classification number: G06F12/1081 ,  G06F3/061 ,  G06F3/0656 ,  G06F3/0683 ,  G06F12/08 ,  G06F12/0875 ,  G06F13/1673 ,  G06F13/28 ,  G06F2212/452 ,  G11C7/1072

Abstract: The invention provides the data flow communication control between the source (flash/IO) and destination (IO/flash) cores. The source and destination cores are started simultaneously instead of serially and get instructions from the descriptors provided and set-up by the processor. Each source and destination core's descriptors1 are correlated or tied with each other by the processor by providing information to the hardware assist mechanism. The hardware assist mechanism responsible for moderating the data transfer from source to destination. The flow tracker guarantees that data needed by destination exists. 1 Descriptors are set of instructions that is used to activate the DMA controller.By applying the invention to the prior approach/solution, the data latency between the flash & IO bus will be reduced. Processor interrupts will be minimized while data transfer between the flash & IO bus is ongoing.

Abstract translation: 本发明提供了源（闪存/ IO）和目的地（IO /闪存）核之间的数据流通信控制。 源和目标内核同时启动而不是串行启动，并从处理器提供和设置的描述符获取指令。 每个源和目标核心的描述符1通过向硬件辅助机制提供信息由处理器相互关联或相互关联。 硬件辅助机制负责调节从源到目的地的数据传输。 流量跟踪器保证目的地所需的数据存在。 1描述符是用于激活DMA控制器的指令集。 通过将本发明应用于先前的方法/解决方案，闪存和IO总线之间的数据等待时间将会降低。 闪存和IO总线之间的数据传输正在进行时，处理器中断将被最小化。

公开(公告)号：US09135190B1

公开(公告)日：2015-09-15

申请号：US12876113

申请日：2010-09-04

Applicant: Ricardo H. Bruce ,  Marlon B. Verdan ,  Margaret Anne N. Somera ,  Rowenah Michelle D. Jago-on ,  Maria Eliza B. De Belen ,  Ron Kelvin B. Palacol

Inventor： Ricardo H. Bruce ,  Marlon B. Verdan ,  Margaret Anne N. Somera ,  Rowenah Michelle D. Jago-on ,  Maria Eliza B. De Belen ,  Ron Kelvin B. Palacol

IPC: G06F12/00 ,  G06F13/16 ,  G06F12/02

CPC classification number: G06F13/16 ,  G06F12/02 ,  G06F12/0246

Abstract: The present invention pertains to a multi-profile memory controller and devices that use multi-profile memory controllers. More particularly, the present invention pertains to a multi-profile memory controller and related methods and systems that can operate with memory locations, memory devices, or both which are associated with different memory attributes, different attribute qualifiers, or the like, while minimizing or avoiding some or all of the disadvantages of the prior art.

Abstract translation: 本发明涉及一种多简档存储器控制器和使用多简档存储器控制器的设备。 更具体地说，本发明涉及一种多简档存储器控制器以及可以与存储器位置，存储器件或二者兼容的多个存储器控制器以及与不同的存储器属性，不同的属性限定符等相关联的二者相关联的方法和系统， 避免了现有技术的一些或全部缺点。

公开(公告)号：US09043669B1

公开(公告)日：2015-05-26

申请号：US13475878

申请日：2012-05-18

Applicant: Rey H. Bruce ,  Joey B. Climaco ,  Noeme P. Mateo

Inventor： Rey H. Bruce ,  Joey B. Climaco ,  Noeme P. Mateo

IPC: H03M13/00 ,  G11C29/00 ,  H03M13/27 ,  G06F11/10

CPC classification number: G06F11/1076 ,  G06F3/0619 ,  G06F3/064 ,  G06F3/0683 ,  G06F11/1008 ,  G06F11/1048 ,  G06F11/108 ,  G06F13/28 ,  H03M13/27

Abstract: Embodiments of the present invention relate to an apparatus, method, and/or sequence for a distributed ECC that may be used in a storage system. In another embodiment of the invention, an apparatus for handling distributed error correction code (ECC) operations, includes: a plurality of ECC engines configured to perform ECC operations in parallel on multiple data parts; the plurality of ECC engines distributed in parallel to receive some of the multiple data parts that are read from storage media devices and to receive some of the other multiple data parts that are to be written to the storage media devices; and the plurality of ECC engines configured to use respective ECC bytes corresponding to respective ones of the multiple data parts.

Abstract translation: 本发明的实施例涉及可用于存储系统中的分布式ECC的装置，方法和/或顺序。 在本发明的另一个实施例中，一种用于处理分布式纠错码（ECC）操作的装置，包括：多个ECC引擎，被配置为在多个数据部分上并行执行ECC操作; 所述多个ECC引擎并行分布以接收从存储介质设备读取的多个数据部分中的一些，并且接收要写入存储介质设备的其他多个数据部分中的一些; 并且所述多个ECC引擎被配置为使用与所述多个数据部分中的相应数据部分对应的相应的ECC字节。