公开(公告)号：US09778577B2

公开(公告)日：2017-10-03

申请号：US14762837

申请日：2013-12-31

Applicant: CSMC TECHNOLOGIES FAB2 CO., LTD.

Inventor： Wei Huang

IPC: G03F7/20 ,  H01L23/544 ,  G01B11/02 ,  H01L21/66

CPC classification number: G03F7/70625 ,  G01B11/02 ,  H01L22/12 ,  H01L23/544

Abstract: A testing structure of a strip width of a scribing slot is provided, the structure includes a first isolated line (232) and a second isolated line (234) which are perpendicular to each other, the testing structure further includes a first field region pattern (220), the first field region pattern (220) includes two graphics, the two graphics are each located on one side of the first isolated line (232) and opposite to each other. A testing method of a strip width of a scribing slot is also disclosed. Graphics of the field oxide region simulating the LOCOS structure are provided on two sides of the isolated line, the step is artificially generated, a polysilicon gate graphic on a small size source region formed by photolithography can be displayed through online testing of the strip width or online displaying and checking of the strip width, thus a practical situation of the die can be known, an abnormity of the strip width and morphology of the polysilicon gate caused by a reflection of a substrate can be found instantly.

公开(公告)号：US09754795B2

公开(公告)日：2017-09-05

申请号：US15120323

申请日：2015-04-30

Applicant: CSMC TECHNOLOGIES FAB2 CO., LTD.

Inventor： Qiang Hua ,  Yaohui Zhou

IPC: H01L21/02 ,  H01L21/304 ,  H01L21/3105 ,  H01L21/762 ,  H01L21/308 ,  H01L21/311

CPC classification number: H01L21/31056 ,  H01L21/0214 ,  H01L21/02164 ,  H01L21/0217 ,  H01L21/02211 ,  H01L21/02274 ,  H01L21/3081 ,  H01L21/31053 ,  H01L21/31111 ,  H01L21/31116 ,  H01L21/76 ,  H01L21/762

Abstract: A chemical-mechanical polishing process using a silicon oxynitride anti-reflection layer (S340) includes: (S1) providing a semiconductor wafer comprising a substrate (S310), an oxidation layer (S320) formed on the substrate (S310), a silicon nitride layer (S330) formed on the oxidation layer (S320), an anti-reflection layer (S340) formed on the silicon nitride layer (S330), a trench extending through the anti-reflection layer (S340) and into the substrate (S310), and a first silicon dioxide layer (S350) filling the trench and covering the anti-reflection layer (S340); (S2) polishing the first silicon dioxide layer (S350) until the anti-reflection layer (S340) is exposed; (S3) removing the anti-reflection layer (S340) by dry etching; (S4) forming a second silicon dioxide layer (S360) on the surface of the semiconductor wafer from which the anti-reflection layer (S340) is removed; (S5) polishing the second silicon dioxide layer (S360) until the silicon nitride layer (S330) is exposed; (S6) and, removing the silicon nitride layer (S330).

公开(公告)号：US09696371B2

公开(公告)日：2017-07-04

申请号：US14759370

申请日：2013-12-31

Applicant: CSMC TECHNOLOGIES FAB2 CO., LTD.

Inventor： Ming Wang ,  Xiaoqian Lian ,  Yaojun Lin ,  Wenhui Xu ,  Hanshun Chen

IPC: G01R31/02 ,  G01R31/26

CPC classification number: G01R31/2621 ,  G01R31/2623

Abstract: A test method and system for cut-in voltage. The method comprises: coarse scanning of the cut-in voltage: a grid voltage, i.e., the cut-in voltage, is quickly determined when a drain terminal current is greater than a target current for the first time (100); accurate scanning of the cut-in voltage: a scanning step length is shortened continuously until the scanning step length is shorter than a preset step length, and each time the scanning step length is shortened, the scanning is conducted according to the current shortened scanning step length on the basis of the cut-in voltage determined in the former time, and then the cut-in voltage under the condition of the current shortened scanning step length is determined again (200). The scanning voltage is automatically increased or decreased by the test method and system through adding high resolution and high precision test conversion into a second scanning test, and therefore the testing of the cut-in voltage becomes more efficient and more accurate.

公开(公告)号：US09153781B2

公开(公告)日：2015-10-06

申请号：US14355500

申请日：2012-10-22

Applicant: CSMC TECHNOLOGIES FAB2 CO., LTD.

Inventor： Tsung-Nten Hsu ,  Zhaoyu Yang ,  Zhiyong Zhao ,  Chunshan Lu

IPC: H01L21/311 ,  H01L45/00

CPC classification number: H01L45/1633 ,  H01L45/04 ,  H01L45/08 ,  H01L45/1233 ,  H01L45/145 ,  H01L45/146 ,  H01L45/1616 ,  H01L45/1675 ,  H01L45/1683

Abstract: A manufacturing method of a resistive random access storage unit, includes: forming a resistance layer on a first metal layer having a flat surface; forming a passivation layer on the resistance layer; performing an etching process to obtain a plurality of basic units, a basic unit comprising a first metal layer, a resistance layer, and a passivation layer, which are laminated sequentially; depositing a insulating dielectric layer, and flattening the insulating dielectric layer; etching the insulating dielectric layer and the passivation layer to form contacting holes corresponded to the basic units; filling metal wires in the contacting holes; forming a second metal layer. According to the above method, a uniformly distributed resistance can be formed on a whole wafer.

Abstract translation: 一种电阻随机存取存储单元的制造方法，包括：在具有平坦表面的第一金属层上形成电阻层; 在电阻层上形成钝化层; 执行蚀刻处理以获得多个基本单元，包括依次层叠的包括第一金属层，电阻层和钝化层的基本单元; 沉积绝缘介电层，并使绝缘介电层变平; 蚀刻绝缘介电层和钝化层以形成对应于基本单元的接触孔; 在接触孔中填充金属丝; 形成第二金属层。 根据上述方法，可以在整个晶片上形成均匀分布的电阻。

公开(公告)号：US20150126014A1

公开(公告)日：2015-05-07

申请号：US14355500

申请日：2012-10-22

Applicant: CSMC TECHNOLOGIES FAB2 CO., LTD.

Inventor： Tsung-Nten Hsu ,  Zhaoyu Yang ,  Zhiyong Zhao ,  Chunshan Lu

IPC: H01L45/00

CPC classification number: H01L45/1633 ,  H01L45/04 ,  H01L45/08 ,  H01L45/1233 ,  H01L45/145 ,  H01L45/146 ,  H01L45/1616 ,  H01L45/1675 ,  H01L45/1683

Abstract: A manufacturing method of a resistive random access storage unit, includes: forming a resistance layer on a first metal layer having a flat surface; forming a passivation layer on the resistance layer; performing an etching process to obtain a plurality of basic units, a basic unit comprising a first metal layer, a resistance layer, and a passivation layer, which are laminated sequentially; depositing a insulating dielectric layer, and flattening the insulating dielectric layer; etching the insulating dielectric layer and the passivation layer to form contacting holes corresponded to the basic units; filling metal wires in the contacting holes; forming a second metal layer. According to the above method, a uniformly distributed resistance can be formed on a whole wafer.

Abstract translation: 一种电阻随机存取存储单元的制造方法，包括：在具有平坦表面的第一金属层上形成电阻层; 在电阻层上形成钝化层; 执行蚀刻处理以获得多个基本单元，包括依次层叠的包括第一金属层，电阻层和钝化层的基本单元; 沉积绝缘介电层，并使绝缘介电层变平; 蚀刻绝缘介电层和钝化层以形成对应于基本单元的接触孔; 在接触孔中填充金属丝; 形成第二金属层。 根据上述方法，可以在整个晶片上形成均匀分布的电阻。

公开(公告)号：US20140268464A1

公开(公告)日：2014-09-18

申请号：US14357724

申请日：2012-11-09

Applicant: CSMC TECHNOLOGIES FAB2 CO., LTD.

Inventor： Guoding Dai ,  Xiaohui Ma ,  ChaoYao Xue ,  Jian Ou ,  Jing Lu

IPC: H02H9/04

CPC classification number: H02H9/04 ,  H02H7/125 ,  H02M1/32 ,  H02M1/42 ,  Y02B70/12 ,  Y02P80/112

Abstract: An output over-voltage protection circuit for power factor correction, which includes a chip external compensation network, a chip external resistor divider network, a static over-voltage detection circuit, a dynamic over-voltage detection circuit and a compare circuit; The chip external compensation network is connected between the chip external resistor divider network and the dynamic over-voltage detection circuit, the chip external compensation network converts the dynamic over-voltage signal conversion to the dynamic current signal and conveys it to the dynamic over-voltage detection circuit, the dynamic over-voltage detection circuit detects the dynamic current signal and ultimately produces the dynamic over-voltage signal (DYOVP); The dynamic over-voltage signal (DYOVP) is inputted into the compare circuit, which converts the dynamic over-voltage signal (DYOVP) into a voltage compared with a reference voltage and outputs a over-voltage control signal (OVP), so as to achieve a dynamic over-voltage protection function.

Abstract translation: 一种用于功率因数校正的输出过压保护电路，包括芯片外部补偿网络，芯片外部电阻分压网络，静态过电压检测电路，动态过电压检测电路和比较电路; 芯片外部补偿网络连接在芯片外部电阻分压网络和动态过压检测电路之间，芯片外部补偿网络将动态过电压信号转换转换为动态电流信号，并将其传送到动态过电压 检测电路，动态过电压检测电路检测动态电流信号，最终产生动态过电压信号（DYOVP）; 动态过电压信号（DYOVP）被输入到比较电路中，其将动态过电压信号（DYOVP）转换为与参考电压相比的电压，并输出过压控制信号（OVP），以便 实现动态过压保护功能。

公开(公告)号：US08836419B2

公开(公告)日：2014-09-16

申请号：US13807312

申请日：2011-12-07

Applicant: Liang Cheng

Inventor： Liang Cheng

IPC: H03F3/38 ,  H03F3/217 ,  H03K5/24

CPC classification number: H03F3/217 ,  H03F2200/351 ,  H03K5/2481

Abstract: The present disclosure generally relates to a PWM comparator and a class D amplifier. The PWM comparator described above introduces current feedback mechanism, basing the waveform state of received high frequency triangle signal and the level state of output signal of the PWM comparator, the hysteresis is changing dynamically. In the same resolution, the noise resistance ability of the PWM comparator described above is much better than that of the conventional PWM comparators which has a fixed hysteresis, thus the PWM comparator can work stably even if the duty cycle of output signal is nearly 100%.

Abstract translation: 本公开一般涉及PWM比较器和D类放大器。 上述PWM比较器引入电流反馈机制，根据接收的高频三角形信号的波形状态和PWM比较器的输出信号的电平状态，滞后动态变化。 在相同的分辨率下，上述PWM比较器的抗噪声能力比具有固定滞后的常规PWM比较器的抗干扰能力好得多，因此即使输出信号的占空比接近100％，PWM比较器也能稳定工作。 。

公开(公告)号：US20130109146A1

公开(公告)日：2013-05-02

申请号：US13807306

申请日：2011-10-09

Applicant: Le Wang

Inventor： Le Wang

IPC: H01L29/66

CPC classification number: H01L29/66492 ,  H01L29/665 ,  H01L29/6659 ,  H01L29/66636 ,  H01L29/7833

Abstract: A method for fabricating a small-scale MOS device, including: preparing a substrate; forming a first trench in the substrate along a first side of the gate region and forming a second trench in the substrate along a second side of the gate region, the first side of the gate region opposite the second side of the gate region; forming a first lightly doped drain region and a second lightly doped drain region in the first trench and the second trench, respectively; forming a third trench in the substrate overlapping at least a first portion of the first lightly doped drain region and a fourth trench in the substrate overlapping at least a first portion of the second lightly doped drain region; and forming a source region and a drain region in the third trench and the fourth trench, respectively.

Abstract translation: 一种制造小型MOS器件的方法，包括：制备衬底; 在所述栅极区域的第一侧沿所述衬底中形成第一沟槽，并且沿所述栅极区域的第二侧在所述衬底中形成第二沟槽，所述栅极区域的所述第一侧与所述栅极区域的第二侧相对; 在所述第一沟槽和所述第二沟槽中分别形成第一轻掺杂漏极区和第二轻掺杂漏极区; 在所述衬底中形成与所述第一轻掺杂漏极区域的至少第一部分重叠的第三沟槽和所述衬底中的与所述第二轻掺杂漏极区域的至少第一部分重叠的第四沟槽; 以及在第三沟槽和第四沟槽中分别形成源区和漏区。

公开(公告)号：US12272749B2

公开(公告)日：2025-04-08

申请号：US17789628

申请日：2020-09-04

Applicant: CSMC TECHNOLOGIES FAB2 CO., LTD.

Inventor： Jingchuan Zhao ,  Zhili Zhang ,  Sen Zhang

IPC: H01L29/78 ,  H01L29/40 ,  H01L29/66

Abstract: Disclosed are a laterally diffused metal oxide semiconductor device and a method for preparing the same. The device includes a substrate (101) of a first conductivity type, a drift region (102) of a second conductivity type, a longitudinal floating field plate array and a plurality of implantation regions (103) of the first conductivity type. The drift region is located in the substrate of the first conductivity type. The longitudinal floating field plate array includes a plurality of longitudinal floating field plate structures (104) arranged at intervals in rows and columns. Each longitudinal floating field plate structures includes a dielectric layer (1041) disposed on an inner surface of a trench and a conductive layer (1042) filling the trench. The plurality of implantation regions are located in the drift region of, each implantation region is located between two adjacent longitudinal floating field plate structures in each row.

公开(公告)号：US12230693B2

公开(公告)日：2025-02-18

申请号：US17765295

申请日：2020-08-18

Applicant: CSMC TECHNOLOGIES FAB2 CO., LTD.

Inventor： Nailong He ,  Sen Zhang

IPC: H01L21/00 ,  H01L21/04 ,  H01L21/762 ,  H01L29/66 ,  H01L29/78 ,  H01L29/08

Abstract: A semiconductor device and a manufacturing method therefor. The semiconductor device comprises: a semiconductor substrate. A first drift region is formed in the semiconductor substrate. A gate structure is formed on the semiconductor substrate A part of the gate structure covers a part of the first drift region. A first trench is formed in the first drift region, and a drain region is formed in the semiconductor substrate at the bottom of the first trench.