利索-全球专利检索

  1. 登录
  2. 注册

搜索结果

506 条记录 (耗时 0.018 秒)

    MEMS COMPONENTS AND METHOD OF WAFER-LEVEL MANUFACTURING THEREOF
    32.
    发明申请
    MEMS COMPONENTS AND METHOD OF WAFER-LEVEL MANUFACTURING THEREOF 审中-公开
    MEMS组件及其水平制造方法

    公开(公告)号：US20160229685A1

    公开(公告)日：2016-08-11

    申请号：US15024711

    申请日：2014-09-19

    申请人： MOTION ENGINE INC.

    发明人： Robert Mark Boysel

    IPC分类号： B81B7/00 ,  B81C1/00

    CPC分类号： B81B7/007 ,  B81B2201/0235 ,  B81B2201/0242 ,  B81B2201/0264 ,  B81B2207/012 ,  B81B2207/015 ,  B81B2207/07 ,  B81B2207/095 ,  B81C1/00238 ,  B81C2201/013 ,  B81C2203/0792

    摘要： A MEMS and a method of manufacturing MEMS components are provided. The method includes providing a MEMS wafer stack including a top cap wafer, a MEMS wafer and optionally a bottom cap wafer. The MEMS wafer has MEMS structures patterned therein. The MEMS wafer and the cap wafers include insulated conducting channels forming insulated conducting pathways extending within the wafer stack. The wafer stack is bonded to an integrated circuit wafer having electrical contacts on its top side, such that the insulated conducting pathways extend from the integrated circuit wafer to the outer side of the top cap wafer. Electrical contacts on the outer side of the top cap wafer are formed and are electrically connected to the respective insulated conducting channels of the top cap wafer. The MEMS wafer stack and the integrated circuit wafer are then diced into components having respective sealed chambers and MEMS structures housed therein.

    摘要翻译： 提供MEMS和制造MEMS部件的方法。 该方法包括提供包括顶盖晶片，MEMS晶片和任选的底盖晶片的MEMS晶片叠层。 MEMS晶片具有图案化的MEMS结构。 MEMS晶片和盖晶片包括形成在晶片堆叠内延伸的绝缘导电路径的绝缘导电沟道。 晶片堆叠结合到在其顶侧上具有电触点的集成电路晶片，使得绝缘导电路径从集成电路晶片延伸到顶盖晶片的外侧。 形成顶盖晶片外侧的电触点，并与顶盖晶片的相应的绝缘导电通道电连接。 然后将MEMS晶片堆叠和集成电路晶片切割成具有容纳在其中的相应密封室和MEMS结构的部件。

    METHOD FOR PRODUCING A MICROELECTROMECHANICAL DEVICE AND MICROELECTROMECHANICAL DEVICE
    35.
    发明申请
    METHOD FOR PRODUCING A MICROELECTROMECHANICAL DEVICE AND MICROELECTROMECHANICAL DEVICE 审中-公开
    微电子设备和微电子设备的制造方法

    公开(公告)号：US20150219507A1

    公开(公告)日：2015-08-06

    申请号：US14689685

    申请日：2015-04-17

    申请人： Elmos Semiconductor AG

    发明人： Arnd Ten-Have

    IPC分类号： G01L1/16 ,  H01L27/20

    CPC分类号： G01L1/16 ,  B81B2201/0264 ,  B81B2207/015 ,  B81C1/00246 ,  B81C1/00626 ,  B81C2203/0735 ,  G01L9/0047 ,  G01L9/0054 ,  G01L9/0098 ,  H01L27/20 ,  H01L29/66075

    摘要： The invention relates to a method for producing a micro-electromechanical device in a material substrate suitable for producing integrated electronic components, in particular a semiconductor substrate, wherein a material substrate (12,14,16) is provided on which at least one surface structure (26) is to be formed during production of the device. An electronic component (30) is formed in the material substrate (12,14,16) using process steps of a conventional method for producing integrated electronic components. A component element (44) defining the position of the electronic component (30) and/or required for the function of the electronic component (30) is selectively formed on the material substrate (12,14,16) from an etching stop material acting as an etching stop in case of etching of the material substrate (12,14,16) and/or in case of etching of a material layer (52) disposed on the material substrate (12,14,16). When the component element (44) of the electronic component (30) is implemented, a bounding region (48) is also formed on the material substrate (12,14,16) along at least a partial section of an edge of the surface structure (26), wherein said bounding region bounds said partial section. The material substrate (12,14, 16) thus implemented is selectively etched for forming the surface structure (26), in that the edge of the bounding region (48) defines the position of the surface structure (26) to be implemented on the material substrate (12, 14,16).

    摘要翻译： 本发明涉及一种用于在适于生产集成电子部件，特别是半导体衬底的材料衬底中制造微机电器件的方法，其中提供材料衬底（12,14,16），在衬底上提供至少一个表面结构 （26）将在设备的生产期间形成。 使用用于制造集成电子部件的常规方法的工艺步骤，在材料基板（12,14,16）中形成电子部件（30）。 限定电子部件（30）的位置和/或电子部件（30）的功能所需要的部件元件（44）由选择性地形成在材料基板（12,14,16）上的蚀刻停止材料 在蚀刻材料基板（12,14,16）的情况下和/或在蚀刻设置在材料基板（12,14,16）上的材料层（52）的情况下的蚀刻停止）。 当实现电子部件（30）的部件元件（44）时，边界区域（48）也沿表面结构的边缘的至少部分部分形成在材料基板（12,14,16）上 （26），其中所述边界区域限定所述部分部分。 由此实现的材料基板（12,14,16）被选择性地蚀刻以形成表面结构（26），因为边界区域（48）的边缘限定要在其上施加的表面结构（26）的位置 材料基板（12,14,16）。

    ARRANGEMENT OF THROUGH-HOLE STRUCTURES OF A SEMICONDUCTOR PACKAGE
    36.
    发明申请
    ARRANGEMENT OF THROUGH-HOLE STRUCTURES OF A SEMICONDUCTOR PACKAGE 审中-公开
    半导体封装的通孔结构的布置

    公开(公告)号：US20150217995A1

    公开(公告)日：2015-08-06

    申请号：US14129542

    申请日：2013-09-27

    申请人： Weng Hong TEH ,  Sarah K. HANEY ,  Chyi Hwang LIM ,  INTEL CORPORATION

    发明人： Weng Hong Teh ,  Sarah K Haney ,  Chyi Hwang Lim

    IPC分类号： B81C1/00 ,  B81B3/00

    CPC分类号： B81C1/0015 ,  B81B3/0051 ,  B81B2207/015 ,  B81C1/00476 ,  B81C2203/0714 ,  B81C2203/0735 ,  B81C2203/0771 ,  H01L21/568 ,  H01L24/19 ,  H01L24/20 ,  H01L2224/04105 ,  H01L2224/73267

    摘要： A semiconductor package comprising a suspended beam portion including an arrangement of through-hole structures. In an embodiment, a first surface of the suspended beam portion includes edges each defining in part a respective through-hole of a plurality of through-holes extending between the first surface and a second surface. The first surface comprises a plurality of arm portions each located between a respective pair of edge-adjacent edges. The first surface comprises a plurality of node portions each located at a respective junction of three or more of the plurality of arm portions. In another embodiment, for each of the plurality of node portions, a respective total number of arm portions which join one another at the node portion is a number other than four, or two arm portions which join one another at the node portion have respective mid-lines which are oblique to one another.

    摘要翻译： 一种半导体封装，包括包括通孔结构的布置的悬挂梁部分。 在一个实施例中，悬挂梁部分的第一表面包括边缘，每个边缘部分地限定在第一表面和第二表面之间延伸的多个通孔的相应通孔。 第一表面包括多个臂部分，每个臂部分位于相应的一对边缘相邻边缘之间。 第一表面包括多个节点部分，每个节点部分位于多个臂部分中的三个或更多个的相应接合处。 在另一个实施例中，对于多个节点部分中的每个节点部分，在节点部分处彼此连接的臂部分的相应总数是除四个之外的数量，或者在节点部分处彼此连接的两个臂部分分别具有中间 相互倾斜的线条

    Micromechanical device and methods to fabricate same using hard mask resistant to structure release etch
    40.
    发明授权
    Micromechanical device and methods to fabricate same using hard mask resistant to structure release etch 有权
    微机械装置和使用耐掩模结构释放蚀刻的硬掩模制造相同的方法

    公开(公告)号：US09000494B2

    公开(公告)日：2015-04-07

    申请号：US13624307

    申请日：2012-09-21

    申请人： International Business Machines Corporation

    发明人： Michael A. Guillorn ,  Fei Liu ,  Ying Zhang

    IPC分类号： H01L29/84 ,  B81C1/00 ,  H01H1/00

    CPC分类号： B81C1/00396 ,  B81B2201/018 ,  B81B2207/015 ,  B81C1/00476 ,  B81C1/00801 ,  B81C2201/0132 ,  H01H1/0036 ,  H01H1/0094

    摘要： A structure includes a silicon layer disposed on a buried oxide layer that is disposed on a substrate; at least one transistor device formed on or in the silicon layer, the at least one transistor having metallization; a released region of the silicon layer disposed over a cavity in the buried oxide layer; a back end of line (BEOL) dielectric film stack overlying the silicon layer and the at least one transistor device; a nitride layer overlying the BEOL dielectric film stack; a hard mask formed as a layer of hafnium oxide overlying the nitride layer; and an opening made through the layer of hafnium oxide, the layer of nitride and the BEOL dielectric film stack to expose the released region of the silicon layer disposed over the cavity in the buried oxide layer. The hard mask protects the underlying material during a MEMS/NEMS HF vapor release procedure.

    摘要翻译： 一种结构包括设置在设置在基板上的掩埋氧化物层上的硅层; 至少一个晶体管器件形成在硅层上或硅层中，所述至少一个晶体管具有金属化; 所述硅层的释放区域设置在所述掩埋氧化物层中的空腔上方; 覆盖所述硅层和所述至少一个晶体管器件的后端（BEOL）电介质膜堆叠; 覆盖在BEOL电介质膜叠层上的氮化物层; 形成为覆盖氮化物层的氧化铪层的硬掩模; 以及通过氧化铪层，氮化物层和BEOL电介质膜叠层形成的开口，以暴露位于掩埋氧化物层中的空腔上方的硅层的释放区域。 在MEMS / NEMS HF蒸汽释放过程中，硬掩模保护底层材料。