公开(公告)号：US11789791B1

公开(公告)日：2023-10-17

申请号：US18312500

申请日：2023-05-04

Applicant: Rebellions Inc.

Inventor： Seokju Yoon

IPC: G06F9/54 ,  G06F12/1027 ,  G06F12/1009

CPC classification number: G06F9/544 ,  G06F12/1009 ,  G06F12/1027 ,  G06F2212/68

Abstract: A neural processing device and a method for using shared page table thereof are provided. The neural processing device including at least one neural processor, a shared memory shared by the at least one neural processor, and a global interconnection configured to exchange data between the at least one neural processor and the shared memory, comprises at least one processing unit each of which included in each of the at least one neural processor and configured to provide logical addresses, a memory management unit configured to receive and translate the logical addresses into physical addresses, and a physical memory accessible by the physical addresses, wherein the memory management unit comprises a shared page table that has translation information between the logical addresses and the physical addresses and is shared by at least one process with each other.

公开(公告)号：US20230315334A1

公开(公告)日：2023-10-05

申请号：US17708398

申请日：2022-03-30

Applicant: Intel Corporation

Inventor： Abhishek Anil Sharma ,  Wilfred Gomes ,  Rajabali Koduri ,  Pushkar Ranade

IPC: G06F3/06 ,  G06F12/1027

CPC classification number: G06F3/0656 ,  G06F12/1027 ,  G06F3/0673 ,  G06F3/0604 ,  G06F2212/68

Abstract: In one embodiment, an integrated circuit package includes: a first die having a plurality of cores, each of the plurality of cores having a local memory interface circuit to access a local portion of a dynamic random access memory (DRAM); and a second die comprising the DRAM, where at least some of the plurality of cores are directly coupled to a corresponding local portion of the DRAM by a stacking of the first die and the second die. Other embodiments are described and claimed.

公开(公告)号：US20230305965A1

公开(公告)日：2023-09-28

申请号：US18171565

申请日：2023-02-20

Applicant: Apple Inc.

Inventor： Sreevathsa Ramachandra ,  Christopher L. Colletti ,  David E. Kroesche

IPC: G06F12/0891 ,  G06F12/1027 ,  G06F12/0875

CPC classification number: G06F12/0891 ,  G06F12/1027 ,  G06F12/0875 ,  G06F2212/1044 ,  G06F2212/683

Abstract: Techniques are disclosed relating to managing storage array invalidations. A computer system may comprise a processor core configured to operate in an idle state and operate in a run state in which the processor core executes instructions. The computer system may further comprise a power management circuit that is configured to receive, while the processor core is in the idle state, a set of invalidation requests directed to the processor core to invalidate a set of entries of a storage array of the processor core. The power management circuit may store invalidation information indicative of the set of invalidation requests. The power management circuit may determine that the processor core has received a request to transition to the run state. Prior to the processor core operating in the run state, the power management circuit may invalidate the set of entries of the storage array based on the invalidation information.

公开(公告)号：US20230298128A1

公开(公告)日：2023-09-21

申请号：US17849106

申请日：2022-06-24

Applicant: Intel Corporation

Inventor： David Puffer ,  Ankur Shah ,  Niranjan Cooray ,  Aditya Navale ,  David Cowperthwaite

IPC: G06T1/60 ,  G06F12/1027 ,  G06T1/20

CPC classification number: G06T1/60 ,  G06F12/1027 ,  G06T1/20 ,  G06F2212/302 ,  G06F2212/683

Abstract: Embodiments described herein provide techniques to facilitate access to local memory of a graphics processor by a guest software domain. The guest software domain can access the local memory via an address translation system that includes a local memory translation table.

公开(公告)号：US11748254B2

公开(公告)日：2023-09-05

申请号：US17638825

申请日：2019-08-27

Applicant: Ecole Polytechnique Federale de Lausanne (EPFL)

Inventor： Arash Pourhabibi Zarandi ,  Siddharth Gupta ,  Hussein Kassir ,  Mark Sutherland ,  Zilu Tian ,  Mario Paulo Drumond Lages De Oliveira ,  Babak Falsafi ,  Christoph Koch

IPC: G06F12/00 ,  G06F12/02 ,  G06F9/30 ,  G06F12/1027

CPC classification number: G06F12/0238 ,  G06F9/3004 ,  G06F9/30101 ,  G06F12/1027 ,  G06F2212/7201

Abstract: Data transformer apparatus comprising a dispatcher module, a reader module, a converter module and a writer module; the dispatcher module is configured to receive a data transformation request including a first and a second information items; the reader module is configured to retrieve data to be transformed, according to said first information item; obtain the type attribute of the data to be transformed, based on said first information item; send the data to be transformed and the type attribute to the converter module; the converter module is configured to select transformation instructions based on said type attribute; execute, on the data to be transformed, the selected transformation instructions, thereby obtaining transformed data; send the transformed data to the writer module; the writer module is configured to; write the transformed data in an output buffer according to said second information item.

公开(公告)号：US11741018B2

公开(公告)日：2023-08-29

申请号：US17873668

申请日：2022-07-26

Applicant: Intel Corporation

Inventor： David M. Durham ,  Jacob Doweck ,  Michael Lemay ,  Deepak Gupta

IPC: G06F12/10 ,  G06F12/1027

CPC classification number: G06F12/1027 ,  G06F2212/681

Abstract: An apparatus and method for efficient process-based compartmentalization. For example, one embodiment of a processor comprises: execution circuitry to execute instructions and process data; memory management circuitry coupled to the execution circuitry, the memory management circuitry to manage access to a system memory by a plurality of related processes using one or more process-specific translation structures and one or more shared translation structures to be shared by the related processes; and one or more control registers to store a process-specific base address pointer associated with a first process of the plurality of related processes and to store a shared base address pointer to identify the shared translation structures; wherein the memory management circuitry is to use the process-specific base address pointer in combination with a first linear address provided by the first process to walk the process-specific translation structures to identify any permissions and/or physical address associated with the first linear address, wherein if permissions are identified, the memory management circuitry is to use the permissions in place of any permissions specified in the shared translation structures.

公开(公告)号：US11714924B2

公开(公告)日：2023-08-01

申请号：US17469591

申请日：2021-09-08

Applicant: Apple Inc.

Inventor： Manu Gulati ,  Joseph Sokol, Jr. ,  Jeffrey R. Wilcox ,  Bernard J. Semeria ,  Michael J. Smith

IPC: G06F21/72 ,  G06F12/02 ,  G06F12/1027 ,  G06F12/14 ,  G06F21/78 ,  H04L9/08

CPC classification number: G06F21/72 ,  G06F12/0246 ,  G06F12/1027 ,  G06F12/1408 ,  G06F21/78 ,  H04L9/0861 ,  H04L9/0894 ,  G06F2212/7206 ,  G06F2212/7208 ,  G06F2221/2143 ,  H04L2209/12

Abstract: In one embodiment, a system includes a non-volatile memory that may serve as both the main memory system and the backing store (or persistent storage). In some embodiments, the non-volatile memory is divided into a main memory portion and a persistent portion. Data in the main memory operation may be encrypted using one or more first keys, and data in the persistent portion may be encrypted using one or more second keys, in an embodiment. The volatile behavior of main memory may be implemented by discarding the one or more first keys in a power down event or other event that indicates a loss of main memory data, while the one or more second keys may be retained. In one embodiment, the physical address space of the non-volatile memory may be a mapping from a second physical address space that is used within the system.

公开(公告)号：US11714776B2

公开(公告)日：2023-08-01

申请号：US17564975

申请日：2021-12-29

Applicant: TEXAS INSTRUMENTS INCORPORATED

Inventor： Kishon Vijay Abraham Israel Vijayponraj ,  Sriramakrishnan Govindarajan ,  Mihir Narendra Mody

IPC: G06F13/42 ,  G06F9/4401 ,  G06F13/40 ,  G06F12/1027

CPC classification number: G06F13/4247 ,  G06F12/1027 ,  G06F13/4022 ,  G06F2213/0024 ,  G06F2213/0026 ,  G06F2213/0038

Abstract: A system-on-chip (SoC) may be configured to enable a Multi-Chip Daisy Chain Topology using peripheral component interface express (PCIe). The SoC may include a processor, a local memory, a root complex operably connected to the processor and the local memory, and a multi-function endpoint controller. The root complex may obtain forwarding information to configure routing of transactions to one or more PCIe endpoint functions or to the local memory. The root complex may initialize, based on the forwarding information, access between a host and the one or more PCIe endpoint functions. The multi-function endpoint controller may obtain a descriptor and endpoint information to configure outbound portals for transactions to at least one remote host. The multi-function endpoint controller may establish a communication path between the host and a function out of a plurality of functions.

公开(公告)号：US11709782B2

公开(公告)日：2023-07-25

申请号：US17512888

申请日：2021-10-28

Applicant: Arm Limited

Inventor： Paolo Monti ,  Abdel Hadi Moustafa ,  Albin Pierrick Tonnerre ,  Vincenzo Consales ,  Abhishek Raja

IPC: G06F12/10 ,  G06F12/1027

CPC classification number: G06F12/1027 ,  G06F2212/68

Abstract: Circuitry comprises a translation lookaside buffer to store memory address translations, each memory address translation being between an input memory address range defining a contiguous range of one or more input memory addresses in an input memory address space and a translated output memory address range defining a contiguous range of one or more output memory addresses in an output memory address space; in which the translation lookaside buffer is configured selectively to store the memory address translations as a cluster of memory address translations, a cluster defining memory address translations in respect of a contiguous set of input memory address ranges by encoding one or more memory address offsets relative to a respective base memory address; memory management circuitry to retrieve data representing memory address translations from a memory, for storage by the translation lookaside buffer, when a required memory address translation is not stored by the translation lookaside buffer; detector circuitry to detect an action consistent with access, by the translation lookaside buffer, to a given cluster of memory address translations; and prefetch circuitry, responsive to a detection of the action consistent with access to a cluster of memory address translations, to prefetch data from the memory representing one or more further memory address translations of a further set of input memory address ranges adjacent to the contiguous set of input memory address ranges for which the given cluster defines memory address translations.

公开(公告)号：US11693787B2

公开(公告)日：2023-07-04

申请号：US17171185

申请日：2021-02-09

Applicant: TEXAS INSTRUMENTS INCORPORATED

Inventor： Sriramakrishnan Govindarajan ,  Gregory Raymond Shurtz ,  Mihir Narendra Mody ,  Charles Lance Fuoco ,  Donald E. Steiss ,  Jonathan Elliot Bergsagel ,  Jason A.T. Jones

IPC: G06F12/1027 ,  G06F9/455

CPC classification number: G06F12/1027 ,  G06F9/45558 ,  G06F2009/45583 ,  G06F2212/657

Abstract: In an example, a device includes a memory and a processor core coupled to the memory via a memory management unit (MMU). The device also includes a system MMU (SMMU) cross-referencing virtual addresses (VAs) with intermediate physical addresses (IPAs) and IPAs with physical addresses (PAs). The device further includes a physical address table (PAT) cross-referencing IPAs with each other and cross-referencing PAs with each other. The device also includes a peripheral virtualization unit (PVU) cross-referencing IPAs with PAs, and a routing circuit coupled to the memory, the SMMU, the PAT, and the PVU. The routing circuit is configured to receive a request comprising an address and an attribute and to route the request through at least one of the SMMU, the PAT, or the PVU based on the address and the attribute.