Abstract:
This invention relates to an electron source and an image forming apparatus each of which particularly comprises a surface conduction type electron emitting element as an electron emitting element, a method of manufacturing an electron source and an image forming apparatus, in which the energization forming treatment step of the surface conduction type electron emitting element is performed by applying a voltage to an electron emitting portion formation thin film via a nonlinear element connected in series with the thin film and having nonlinear voltage/current characteristics, an electron source and an image forming apparatus in each of which the nonlinear element is connected in series with the surface conduction type electron emitting element, and a method of driving the same.
Abstract:
Fabrication of an electron-emitting device entails distributing electron-emissive carbon-containing particles (22) over a non-insulating region (12). The particles can be made electron emissive after the particle distributing step. Particle bonding material (24) is typically provided to bond the particles to the non-insulating region. The particle bonding material can include carbide formed by heating or/and can be created by modifying a layer (32) provided between the non-insulating region and the particles. In one embodiment, the particles emit electrons primarily from graphite or/and amorphous carbon regions. In another embodiment, the particles are made electron-emissive prior to the particle distributing step.
Abstract:
A flat panel display, such as a Field Emission Display ("FED"), is disclosed having a current control circuit. Input into the display, initially, is an analog signal having an amplitude. In one embodiment, the current control circuit includes a converter for converting the analog input signal to a sawtooth signal having a height and width. Then, the level of the sawtooth signal is compared to a voltage level to establish a pulse width of an emitter current. The emitter current is thus controlled by a pulse width modulation approach. In another embodiment, the current control circuit traps a column voltage on a parasitic capacitance. The trapped voltage then controls the gate of a transistor to control current flow from the emitter set to ground.
Abstract:
An amorphous multi-layered structure (100, 200) is formed by a method including the steps of: i) positioning a deposition substrate (101) in a physical vapor deposition apparatus (300, 400, 500) ii) ionizing a precursor of a multi-phase material within the physical vapor deposition apparatus (300, 400, 500) iv) modulating the total ion impinging energy of the ions to deposit layers having predetermined properties corresponding to the total ion impinging energy values.
Abstract:
A field emitter display having reduced surface leakage comprising at least one emitter tip surrounded by a dielectric region. The dielectric region is formed of a composite of insulative layers, at least one of which has fins extending toward the emitter tip. A conductive gate, for extracting electrons from the emitter tip, is disposed superjacent the dielectric region. The fins increase the length of the path that leaked electrical charge travels before impacting the gate.
Abstract:
A matrix field-emission cathode (5) comprises a monocrystalline silicon substrate (7) on which are arranged epitaxially grown pointed silicon emitters (1) which also act as ballast resistors connected in series to the emitters. In an advantageous embodiment of the proposed cathode, for a radius of curvature (r) at the emitter tip not exceeding 10 nm, the ratio of the height (h) of the emitter to the radius (r) is not less than 1000, while the ratio of height (h) to the diameter (D) at the emitter base is not less than 1. The angle .alpha. at the emitter tip does not exceed 30.degree.. The specific resistance of the emitter material is chosen so as to ensure that the resistance of each emitter will be comparable with the resistance between the cathode and the opposing electrode. The proposed cathode is used in an electronic device for displaying information which also has an anode (3) in the form of a strip (11) of phosphorescent material (10) and a conducting layer (9) whose projection onto the cathode (5) is perpendicular to the conducting paths (6) on the cathode; the anode itself acts as the control electrode.
Abstract:
A gated filament structure for a field emission display includes a plurality of filaments. Included is a substrate, an insulating layer positioned adjacent to the substrate, and a metal gate layer position adjacent to the insulating layer. The metal gate layer has a plurality of gates, the metal gate layer having an average thickness "s" and a top metal gate layer planar surface that is substantially parallel to a bottom metal gate layer planar surface. The metal gate layer includes a plurality of apertures extending through the gates. Each aperture has an average width "r" along a bottom planar surface of the aperture. Each aperture defines a midpoint plane positioned parallel to and equally distant from the top metal gate layer planar surface and the bottom metal gate layer planar surface. A plurality of filaments are individually positioned in an aperture. Each filament has a filament axis. The intersection of the filament axis and the midpoint plane defines a point "O". Each filament includes a filament tip terminating at a point "A". A majority of all filament tips of the display have a length "L" between each filament tip at point A and point O along the filament axis where, L.ltoreq.(s+r)/2.
Abstract:
An emitter structure 12 for use in a field emission display device comprises a ballast layer 17 overlying an electrically conductive coating 16 (cathode electrode), which is itself formed on an electrically insulating substrate 18. A gate electrode comprises a coating of an electrically conductive material 22 which is deposited on an insulating layer 20. Cone-shaped microtips 14 formed within apertures 34 through conductive layer 22 and insulating layer 20. In the present invention, insulating layer 20 comprises a dielectric material capable of desorbing at least ten atomic percent hydrogen, which may illustratively comprise hydrogen silsesquioxane (HSQ). HSQ is an abundant source of hydrogen which keeps deleterious oxides from forming on microtip emitters 14. HSQ also reduces the capacitance formed by cathode electrode 16 and gate electrode 22, since its relative dielectric constant is less than 3.5. In alternative embodiments, the gate insulation layer 20 additionally includes one or more sublayers of a more dense insulating material 20b and 20c, typically a plasma deposited silicon dioxide.
Abstract:
A field emission cold cathode includes a conductive substrate (1), an insulating layer (2) disposed on the substrate (1), a gate electrode (3) disposed on the insulating layer (2), cavities (4) extending through the gate electrode (3) and the insulating layer (2), and emitter cones (6) disposed on the substrate (1) within the cavities (4). The gate electrode further includes high resistance areas (5) disposed around the tips of the emitter cones (6) that enables the field emission cold cathode to operate in the event of a short circuit between the gate electrode (3) and an emitter cone (6) due to electrically conductive foreign material entering a cavity (4). The field emission cold cathode can be use in an electron gun.
Abstract:
A microtip of a field emission device cathode (10) may be fabricated by forming a dielectric layer (18) on an upper surface of a resistive layer (16). A gate layer (20) is formed on the dielectric layer (18). An opening is formed in the gate layer (20) and a microtip cavity (28) is formed in the dielectric layer (18). The microtip cavity (28) extends through the opening in the gate layer (20) to the resistive layer (16). Layers of metal are formed on the gate layer (20) and the resistive layer (16) such that a microtip (30) is formed within the microtip cavity (28). Finally, polishing is performed to remove a portion of the overburden or layers of metal on the gate layer (20). The polishing continues until the microtip (30) is exposed.