公开(公告)号：US20140239387A1

公开(公告)日：2014-08-28

申请号：US13776370

申请日：2013-02-25

申请人： TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.

发明人： Po-Yu Chen

IPC分类号： H01L21/82 ,  H01L27/088

CPC分类号： H01L21/823487 ,  H01L21/265 ,  H01L21/283 ,  H01L21/30604 ,  H01L21/31 ,  H01L21/31116 ,  H01L21/3213 ,  H01L21/32133 ,  H01L21/76879 ,  H01L21/823475 ,  H01L27/088 ,  H01L29/4236 ,  H01L29/45 ,  H01L29/66666

摘要： A MOS transistor structure comprises a substrate including a bulk semiconductor region, a first gate formed in a first trench, a first drain/source region, a second drain/source region, wherein the first drain/source region and the second drain/source region are formed on opposing sides of the first gate. The MOS transistor structure further comprises a second gate formed in a second trench, a third drain/source region, wherein the third drain/source region and the second drain/source region are formed on opposing sides of the second gate and a channel region formed in the bulk semiconductor region, wherein the channel region, the first drain/source region, the second drain/source region and the third drain source region share a same polarity.

摘要翻译： MOS晶体管结构包括包括体半导体区域的基板，形成在第一沟槽中的第一栅极，第一漏极/源极区域，第二漏极/源极区域，其中第一漏极/源极区域和第二漏极/源极区域 形成在第一门的相对侧上。 MOS晶体管结构还包括形成在第二沟槽中的第二栅极，第三漏极/源极区域，其中第三漏极/源极区域和第二漏极/源极区域形成在第二栅极的相对侧上，并且形成沟道区域 在体半导体区域中，其中沟道区域，第一漏极/源极区域，第二漏极/源极区域和第三漏极源极区域具有相同的极性。

公开(公告)号：US08460569B2

公开(公告)日：2013-06-11

申请号：US13081692

申请日：2011-04-07

申请人： Ludovic Godet ,  Christopher R. Hatem ,  Patrick M. Martin ,  Timothy J. Miller

发明人： Ludovic Godet ,  Christopher R. Hatem ,  Patrick M. Martin ,  Timothy J. Miller

IPC分类号： B44C1/22 ,  C03C15/00 ,  C03C25/68 ,  C23F1/00

CPC分类号： H01L21/306 ,  H01L21/2658 ,  H01L21/26586 ,  H01L21/3105 ,  H01L21/311 ,  H01L21/31155 ,  H01L21/321 ,  H01L21/3213

摘要： A method of patterning a substrate, comprises providing a set of patterned features on the substrate, exposing the set of patterned features to a dose of ions incident on the substrate over multiple angles, and selectively etching exposed portions of the patterned features.

摘要翻译： 图案化衬底的方法包括在衬底上提供一组图案化特征，将一组图案化特征暴露于在多个角度上入射到衬底上的一定剂量的离子，以及选择性地蚀刻图案化特征的暴露部分。

公开(公告)号：US20120258600A1

公开(公告)日：2012-10-11

申请号：US13081692

申请日：2011-04-07

申请人： Ludovic Godet ,  Christopher R. Hatem ,  Patrick M. Martin ,  Timothy J. Miller

发明人： Ludovic Godet ,  Christopher R. Hatem ,  Patrick M. Martin ,  Timothy J. Miller

IPC分类号： H01L21/306

CPC分类号： H01L21/306 ,  H01L21/2658 ,  H01L21/26586 ,  H01L21/3105 ,  H01L21/311 ,  H01L21/31155 ,  H01L21/321 ,  H01L21/3213

摘要： A method of patterning a substrate, comprises providing a set of patterned features on the substrate, exposing the set of patterned features to a dose of ions incident on the substrate over multiple angles, and selectively etching exposed portions of the patterned features.

摘要翻译： 图案化衬底的方法包括在衬底上提供一组图案化特征，将一组图案化特征暴露于在多个角度上入射到衬底上的一定剂量的离子，以及选择性地蚀刻图案化特征的暴露部分。

公开(公告)号：US20080045009A1

公开(公告)日：2008-02-21

申请号：US11844459

申请日：2007-08-24

申请人： Dinesh Chopra

发明人： Dinesh Chopra

IPC分类号： H01L21/4763

CPC分类号： H01L21/3213 ,  B23H5/08 ,  C25F3/02 ,  C25F3/30 ,  C25F7/00 ,  H01L21/32115 ,  H01L21/32125 ,  H01L21/32134 ,  H01L21/7684

摘要： A method and apparatus for simultaneously removing conductive materials from a microelectronic substrate. A method in accordance with one embodiment of the invention includes contacting a surface of a microelectronic substrate with an electrolytic liquid, the microelectronic substrate having first and second different conductive materials. The method can further include controlling a difference between a first open circuit potential of the first conducive material and a second open circuit potential of the second conductive material by selecting a pH of the electrolytic liquid. The method can further include simultaneously removing at least portions of the first and second conductive materials by passing a varying electrical signal through the electrolytic liquid and the conductive materials. Accordingly, the effects of galvanic interactions between the two conductive materials can be reduced and/or eliminated.

摘要翻译： 一种用于从微电子衬底同时去除导电材料的方法和装置。 根据本发明的一个实施例的方法包括使微电子衬底的表面与电解液接触，微电子衬底具有第一和第二不同的导电材料。 该方法还可以包括通过选择电解液的pH来控制第一导电材料的第一开路电位和第二导电材料的第二开路电位之间的差。 该方法还可以包括通过使变化的电信号通过电解液和导电材料同时去除第一和第二导电材料的至少一部分。 因此，可以减少和/或消除两种导电材料之间的电偶相互作用的影响。

公开(公告)号：US20050045994A1

公开(公告)日：2005-03-03

申请号：US10952056

申请日：2004-09-28

申请人： Colin Gormley ,  Stephen Brown ,  Scott Blackstone

发明人： Colin Gormley ,  Stephen Brown ,  Scott Blackstone

IPC分类号： G02B26/08 ,  H01L21/00 ,  H01L21/20 ,  H01L21/311 ,  H01L21/3213 ,  H01L21/44 ,  H01L21/46 ,  H01S5/02

CPC分类号： H01L21/3213 ,  G02B26/0833 ,  H01L21/311

摘要： A method for forming a multi-layer semiconductor device (1) having a lower silicon layer (4), an intermediate silicon layer (5) within which micro-mirrors (10) are formed and an upper spacer layer (6) of silicon for spacing another component from the micro-mirrors (10). First and second etch stop layers (8, 9) of oxide act as insulation between the respective layers (4, 5, 6). In order to minimise damage to the micro-mirrors (10), the formation of the micro-mirrors (10) is left to the end of the forming process. An assembly of the lower layer (4) and the intermediate layer (5) with the fist etch stop layer (8) is formed, and the second etch stop layer (9) is than grown and patterned on the intermediate layer (5) for subsequent formation of the micro-mirrors (10). The upper layer (5) is then bonded by an annealing process to the is patterned second etch stop layer (9). After the formation of communicating bores (30) in the lower layer (4) and thinning of the fist etch stop layer (8) adjacent the micro-mirrors (10) through the communicating bores (30), openings (16) in the upper layer (6) and the micro-mirrors (10) are sequentially formed by reactive ion etching through the upper layer (6). Portions of the first and second etch stop layers (8, 9) adjacent the micro-mirrors (10) am then etched away.

摘要翻译： 一种用于形成具有下硅层（4）的多层半导体器件（1），形成有微镜（10）的中间硅层（5）和用于硅的上间隔层（6）的多层半导体器件（1）的方法， 将另一组件与微反射镜（10）间隔开。 氧化物的第一和第二蚀刻停止层（8,9）用作各层（4,5,6）之间的绝缘体。 为了最小化对微反射镜（10）的损伤，微反射镜（10）的形成留在成型过程的结束。 形成具有第一蚀刻停止层（8）的下层（4）和中间层（5）的组件，并且第二蚀刻停止层（9）不在中间层（5）上生长和图案化，用于 随后形成微镜（10）。 然后通过退火工艺将上层（5）结合到图案化的第二蚀刻停止层（9）上。 在下层（4）中形成连通孔（30）并且通过连通孔（30）使靠近微反射镜（10）的第一蚀刻停止层（8）变薄，上部的开口（16） 层（6）和微反射镜（10）通过上层（6）的反应离子蚀刻顺序地形成。 邻近微反射镜（10）的第一和第二蚀刻停止层（8,9）的部分然后蚀刻掉。

公开(公告)号：US20050020004A1

公开(公告)日：2005-01-27

申请号：US10923359

申请日：2004-08-20

申请人： Dinesh Chopra

发明人： Dinesh Chopra

IPC分类号： B23H5/08 ,  C25F3/02 ,  C25F7/00 ,  H01L21/321 ,  H01L21/326 ,  H01L21/768 ,  H01L21/78 ,  H01L21/8238

CPC分类号： H01L21/3213 ,  B23H5/08 ,  C25F3/02 ,  C25F3/30 ,  C25F7/00 ,  H01L21/32115 ,  H01L21/32125 ,  H01L21/32134 ,  H01L21/7684

摘要： A method and apparatus for simultaneously removing conductive materials from a microelectronic substrate. A method in accordance with one embodiment of the invention includes contacting a surface of a microelectronic substrate with an electrolytic liquid, the microelectronic substrate having first and second different conductive materials. The method can further include controlling a difference between a first open circuit potential of the first conducive material and a second open circuit potential of the second conductive material by selecting a pH of the electrolytic liquid. The method can further include simultaneously removing at least portions of the first and second conductive materials by passing a varying electrical signal through the electrolytic liquid and the conductive materials. Accordingly, the effects of galvanic interactions between the two conductive materials can be reduced and/or eliminated.

摘要翻译： 一种用于从微电子衬底同时去除导电材料的方法和装置。 根据本发明的一个实施例的方法包括使微电子衬底的表面与电解液接触，微电子衬底具有第一和第二不同的导电材料。 该方法还可以包括通过选择电解液的pH来控制第一导电材料的第一开路电位和第二导电材料的第二开路电位之间的差。 该方法还可以包括通过使变化的电信号通过电解液和导电材料同时去除第一和第二导电材料的至少一部分。 因此，可以减少和/或消除两种导电材料之间的电偶相互作用的影响。

公开(公告)号：US06613667B1

公开(公告)日：2003-09-02

申请号：US10139129

申请日：2002-05-02

申请人： Yue Kuo

发明人： Yue Kuo

IPC分类号： H01L214763

CPC分类号： H01L21/76838 ,  H01L21/32115 ,  H01L21/3213 ,  H01L21/32134 ,  H01L21/4763

摘要： Forming an interconnect of a semiconductor device includes defining a recessed structure proximate to an outer surface of a substrate of a semiconductor device. A metal layer is deposited within the recessed structure. A region of the metal layer is exposed to a plasma operable to react with the region of the metal layer. A metal compound layer is formed from the region of the metal layer by reacting the region of the metal layer with the plasma. The metal compound layer is removed from the semiconductor structure to yield a remaining metal layer. An interconnect of the semiconductor device is formed from the remaining metal layer.

摘要翻译： 形成半导体器件的互连包括限定靠近半导体器件的衬底的外表面的凹陷结构。 金属层沉积在凹陷结构内。 金属层的区域暴露于可操作以与金属层的区域反应的等离子体。 通过使金属层的区域与等离子体反应，由金属层的区域形成金属化合物层。 从半导体结构中去除金属化合物层以产生剩余的金属层。 半导体器件的互连由剩余的金属层形成。

公开(公告)号：US6130165A

公开(公告)日：2000-10-10

申请号：US997499

申请日：1997-12-23

申请人： Emilio Camerlenghi ,  Elio Colabella ,  Luca Pividori ,  Adriana Rebora

发明人： Emilio Camerlenghi ,  Elio Colabella ,  Luca Pividori ,  Adriana Rebora

IPC分类号： H01L21/302 ,  H01L21/3065 ,  H01L21/3213 ,  H01L21/768 ,  H01L21/8247 ,  H01L27/115 ,  H01L29/788 ,  H01L29/792 ,  H01L21/311

CPC分类号： H01L27/11521 ,  H01L21/3213 ,  H01L21/76838

摘要： Self-aligned etching process for providing a plurality of mutually parallel word lines in a first conducting layer deposited over a planarized architecture obtained starting from a semiconductor substrate on which is provided a plurality of active elements extending along separate parallel lines e.g., memory cell bit lines and comprising gate regions made up of a first conducting layer, an intermediate dielectric layer and a second conducting layer with said regions being insulated from each other by insulation regions to form said architecture with said word lines being defined photolithographically by protective strips implemented by means of: a vertical profile etching for complete removal from the unprotected areas of the first conducting layer of the second conducting layer and of the intermediate dielectric layer respectively, and a following isotropic etching of the first conducting layer.

摘要翻译： 自对准蚀刻工艺，用于在由半导体衬底开始沉积的第一导电层中沉积的第一导电层中提供多个相互平行的字线，所述半导体衬底上设置有沿着分离的并行线延伸的多个有源元件，例如存储器单元位线 并且包括由第一导电层，中间电介质层和第二导电层构成的栅极区，其中所述区域通过绝缘区域彼此绝缘以形成所述结构，所述字线通过防护带光刻地限定， ：用于从第二导电层和中间介电层的第一导电层的未保护区域完全去除的垂直轮廓刻蚀，以及第一导电层的以下各向同性蚀刻。

公开(公告)号：US6103633A

公开(公告)日：2000-08-15

申请号：US977190

申请日：1997-11-24

申请人： Yun-Hung Shen ,  Sheng-Liang Pan

发明人： Yun-Hung Shen ,  Sheng-Liang Pan

IPC分类号： H01L21/3205 ,  H01L21/3213 ,  H01L21/768 ,  H01L21/00

CPC分类号： H01L21/76862 ,  H01L21/32051 ,  H01L21/3213 ,  H01L21/76841 ,  H01L21/76858

摘要： A new method of cleaning metal precipitates after the etching of metal lines using a two-step process is described. Semiconductor device structures are provided in and on a semiconductor substrate. The semiconductor device structures are covered with an insulating layer. A barrier metal layer is deposited overlying the insulating layer. A metal layer is deposited overlying the barrier metal layer wherein metal precipitates form at the interface between the barrier metal layer and the metal layer. The metal layer is covered with a layer of photoresist which is exposed to actinic light and developed and patterned to form the desired photoresist mask. The metal layer is etched away where it is not covered by the photoresist mask to form metal lines whereby the metal precipitates are exposed on the surface of the barrier metal layer. The barrier metal layer is anisotropically etched into using a high DC bias of greater than 240 volts and thereafter isotropically etched into underlying the metal precipitates whereby the metal precipitates are stripped away from the surface of the barrier metal layer completing the cleaning of the metal precipitates in the formation of metal lines in the fabrication of an integrated circuit.

摘要翻译： 描述了在使用两步法蚀刻金属线之后清洗金属沉淀物的新方法。 半导体器件结构设置在半导体衬底中和半导体衬底上。 半导体器件结构被绝缘层覆盖。 覆盖在绝缘层上的阻挡金属层被沉积​​。 金属层沉积在阻挡金属层上，其中金属沉淀物在阻挡金属层和金属层之间的界面处形成。 金属层被一层光致抗蚀剂覆盖，该光致抗蚀剂暴露于光化光并显影和图案化以形成所需的光致抗蚀剂掩模。 金属层被蚀刻掉，其未被光致抗蚀剂掩模覆盖以形成金属线，由此金属沉淀物暴露在阻挡金属层的表面上。 阻挡金属层被各向异性地蚀刻成使用大于240伏特的高直流偏压，然后各向同性蚀刻到金属沉淀物的下面，从而将金属沉淀物从阻挡金属层的表面剥离，完成金属沉淀物的清洁 在制造集成电路中形成金属线。

公开(公告)号：US6087266A

公开(公告)日：2000-07-11

申请号：US883860

申请日：1997-06-27

申请人： Susan C. Abraham

发明人： Susan C. Abraham

IPC分类号： H01L21/302 ,  H01L21/3213

CPC分类号： H01J37/32174 ,  H01L21/3213 ,  H01L21/32136 ,  H01J2237/0206

摘要： A method for improving microloading of a substrate to be etched in a plasma processing chamber. The substrate is etched with a first etchant to form trenches having a given trench width. The plasma processing chamber has a first power supply configured to energize a first electrode of the chamber and a second power supply configured to energize a second electrode of the chamber. The method includes obtaining a first data set among a plurality of data sets correlating power ratios of the first power supply and the second power supply with microloading percentages for the first etchant for different trench widths. The first data set correlates the power ratios with the microloading percentages for a first trench width. The first trench width approximates the given trench width as closely as possible. The method also includes extrapolating a second data set from the first data set. The second data set correlates the power ratios with the microloading percentages for the given trench width. There is also included ascertaining a power ratio of the power ratios of the second data set that yields a desired level of microloading. Additionally, there is included setting a first setting of one of the first power supply and the second power supply in accordance with the power ratio to achieve the desired level of microloading.

摘要翻译： 一种用于改善在等离子体处理室中要蚀刻的基板的微加载的方法。 用第一蚀刻剂蚀刻衬底以形成具有给定沟槽宽度的沟槽。 等离子体处理室具有被配置为激励室的第一电极的第一电源和被配置为对腔室的第二电极通电的第二电源。 该方法包括获得多个数据集中的第一数据集，其将第一电源和第二电源的功率比与用于不同沟槽宽度的第一蚀刻剂的微加载百分比相关联。 第一数据集将功率比与第一沟槽宽度的微负载百分比相关联。 第一沟槽宽度尽可能接近于给定的沟槽宽度。 该方法还包括从第一数据集外推第二数据集。 第二数据集将功率比与给定沟槽宽度的微载荷百分比相关联。 还包括确定产生期望的微负载水平的第二数据集的功率比的功率比。 此外，包括根据功率比来设置第一电源和第二电源中的一个的第一设置，以实现期望的微负载水平。