公开(公告)号：US09899318B2

公开(公告)日：2018-02-20

申请号：US15432342

申请日：2017-02-14

申请人： INTERNATIONAL BUSINESS MACHINES CORPORATION

发明人： Chih-Chao Yang

IPC分类号： H01L23/52 ,  H01L23/525 ,  H01L23/532

CPC分类号： H01L23/5252 ,  H01L23/53209 ,  H01L23/53223 ,  H01L23/53238 ,  H01L23/53257 ,  H01L23/53266

摘要： An antifuse structure including a first electrode that is present in at a base of the opening in the dielectric material. The antifuse structure further includes an antifuse material layer comprising a phase change material alloy of tantalum and nitrogen. A first surface of the antifuse material layer is present in direct contact with the first electrode. A second electrode is present in direct contact with a second surface of the antifuse material layer that is opposite the first surface of the antifuse material layer.

公开(公告)号：US09899100B2

公开(公告)日：2018-02-20

申请号：US15599241

申请日：2017-05-18

申请人： Magnachip Semiconductor, Ltd.

发明人： Duk Ju Jeong ,  Su Jin Kim

IPC分类号： G11C17/00 ,  G11C17/16 ,  H01L23/525 ,  H01L29/49 ,  H01L27/112 ,  H01L49/02 ,  H01L23/528 ,  G11C17/18 ,  H01L29/423

CPC分类号： G11C17/165 ,  G11C17/16 ,  G11C17/18 ,  H01L23/5252 ,  H01L23/528 ,  H01L27/11206 ,  H01L28/40 ,  H01L29/42368 ,  H01L29/4975 ,  H01L29/78

摘要： An anti-fuse device includes a gate insulating film formed on a semiconductor substrate, a gate electrode formed on the gate insulating film, and a salicide layer formed on a first portion of the gate electrode such that a second portion of the gate electrode omits the salicide layer, wherein a hard breakdown of at least a portion of the gate insulating film at a time of programming the anti-fuse device.

公开(公告)号：US09887203B2

公开(公告)日：2018-02-06

申请号：US15222832

申请日：2016-07-28

申请人： Monolithic 3D Inc.

发明人： Zvi Or-Bach ,  Zeev Wurman

IPC分类号： H03K19/173 ,  H01L27/112 ,  H01L23/525

CPC分类号： H01L27/1128 ,  G06F17/505 ,  G06F17/5068 ,  H01L21/768 ,  H01L23/5252 ,  H01L27/11206 ,  H01L2224/16225 ,  H01L2224/32145 ,  H01L2224/32225 ,  H01L2224/48091 ,  H01L2224/48227 ,  H01L2224/73204 ,  H01L2224/73265 ,  H01L2924/1305 ,  H03K19/17736 ,  H03K19/17748 ,  H03K19/1778 ,  H01L2924/00014 ,  H01L2924/00

摘要： A 3D semiconductor device including: a first layer including a first monocrystalline layer, the first layer including first logic cells; a second layer including a monocrystalline semiconductor layer, the second layer overlying the first layer, the second layer including second transistors, where the logic cells include a Look-Up-Table logic cell, and where the second transistors are aligned to the first logic cells with less than 200 nm alignment error.

公开(公告)号：US09887202B2

公开(公告)日：2018-02-06

申请号：US15334411

申请日：2016-10-26

申请人： Samsung Electronics Co., Ltd.

发明人： Hyun-Min Choi ,  Shigenobu Maeda ,  Jihoon Yoon ,  Sungman Lim

IPC分类号： H01L29/78 ,  H01L27/112 ,  H01L29/06 ,  H01L29/423 ,  H01L23/522 ,  H01L23/525 ,  H01L27/02

CPC分类号： H01L27/11206 ,  H01L23/5226 ,  H01L23/5252 ,  H01L27/0207 ,  H01L29/0649 ,  H01L29/0653 ,  H01L29/42372 ,  H01L29/785 ,  H01L29/7851

摘要： The inventive concepts provide semiconductor devices and methods of manufacturing the same. One semiconductor device includes a substrate, a device isolation layer disposed on the substrate, a fin-type active pattern defined by the device isolation layer and having a top surface higher than a top surface of the device isolation layer, a first conductive line disposed on an edge portion of the fin-type active pattern and on the device isolation layer adjacent to the edge portion of the fin-type active pattern, and an insulating thin layer disposed between the fin-type active pattern and the first conductive line. The first conductive line forms a gate electrode of an anti-fuse that may be applied with a write voltage.

公开(公告)号：US09887201B2

公开(公告)日：2018-02-06

申请号：US15250831

申请日：2016-08-29

申请人： Kilopass Technology, Inc.

发明人： Harry Shengwen Luan

IPC分类号： H01L27/112 ,  H01L21/28 ,  G11C17/16 ,  H01L23/525 ,  H01L29/66

CPC分类号： H01L27/11206 ,  G11C17/16 ,  H01L21/28008 ,  H01L23/5252 ,  H01L29/66477 ,  H01L2924/0002 ,  H01L2924/00

摘要： A one time programmable nonvolatile memory formed from metal-insulator semiconductor cells. The cells are at the crosspoints of conductive gate lines and intersecting lines formed in a semiconductor substrate. Among others, features include forming the gate lines with polysilicon layers of one conductivity type and the intersecting lines with dopants of the opposite conductivity type in the substrate; forming the intersecting lines with differing dopant concentrations near the substrate surface and deeper in the substrate; and forming the widths of the gate lines and intersecting lines with the minimum feature size that can be patterned by a particular semiconductor technology.

公开(公告)号：US20180033795A1

公开(公告)日：2018-02-01

申请号：US15661776

申请日：2017-07-27

申请人： Synopsys, Inc.

发明人： Andrew E. Horch ,  Martin L. Niset ,  Ting-Jia Hu

IPC分类号： H01L27/112 ,  H01L23/525 ,  H01L23/528 ,  G11C17/18 ,  H01L29/423 ,  H01L29/06 ,  G11C17/16 ,  H01L29/08 ,  H01L29/10

CPC分类号： H01L27/11206 ,  G11C17/16 ,  G11C17/18 ,  H01L23/5252 ,  H01L23/528 ,  H01L29/0649 ,  H01L29/0847 ,  H01L29/1033 ,  H01L29/42364

摘要： An OTP memory device includes a first and a second doped region of the same polarity in a semiconductor substrate. The second doped region has a higher doping concentration than the first doped region. A source region and a drain region of an opposite polarity are also in the semiconductor substrate. The source is positioned over the lower doped region, and the drain is positioned over the higher doped region. A plurality of anti-fuse devices, separated from each other by a portion of the lower doped region, are each positioned at least partially above a respective portion of the source region (and, in turn, above the lower doped region). A first metal line is coupled to a first subset of the anti-fuse devices, and a second metal line is coupled to a different, second subset of the anti-fuse devices arranged between the anti-fuses in the first subset.

公开(公告)号：US20180019248A1

公开(公告)日：2018-01-18

申请号：US15553465

申请日：2016-02-19

申请人： Floadia Corporation

发明人： Hideo KASAI ,  Yasuhiro TANIGUCHI ,  Yasuhiko KAWASHIMA ,  Ryotaro SAKURAI ,  Yutaka SHINAGAWA ,  Tatsuro TOYA ,  Takanori YAMAGUCHI ,  Fukuo OWADA ,  Shinji YOSHIDA ,  Teruo HATADA ,  Satoshi NODA ,  Takafumi KATO ,  Tetsuya MURAYA ,  Kosuke OKUYAMA

IPC分类号： H01L27/112 ,  H01L23/525

CPC分类号： H01L27/11206 ,  G11C17/16 ,  H01L23/5252

摘要： In a semiconductor memory device, voltage application from a memory gate electrode of the memory capacitor to a word line can be blocked by a rectifier element depending on values of voltages applied to the memory gate electrode and the word line without using a conventional control circuit. The configuration eliminates the need to provide a switch transistor and a switch control circuit for turning on and off the switch transistor as in conventional cases, and accordingly achieves downsizing. In the semiconductor memory device, for example, each bit line contact is shared by four anti-fuse memories adjacent to each other and each word line contact is shared by four anti-fuse memories adjacent to each other, thereby achieving downsizing of the entire device as compared to a case in which the bit line contact and the word line contact are individually provided to each anti-fuse memory.

公开(公告)号：US20180005704A1

公开(公告)日：2018-01-04

申请号：US15631263

申请日：2017-06-23

申请人： Renesas Electronics Corporation

发明人： Hiromichi TAKAOKA

IPC分类号： G11C17/16 ,  H01L27/112 ,  H01L23/528 ,  H01L23/525 ,  H01L29/06 ,  G11C17/18

CPC分类号： G11C17/165 ,  G11C17/16 ,  G11C17/18 ,  H01L23/5252 ,  H01L23/528 ,  H01L27/11206 ,  H01L29/0649 ,  H01L29/0684

摘要： There is to provide a semiconductor device capable of improving the reliability. The semiconductor device is provided with an anti-fuse element including a semiconductor substrate, a well region of a first conductivity type formed in the semiconductor substrate, and a gate electrode formed over the semiconductor substrate through a gate insulating film, and source regions of a second conductivity type opposite to the first conductivity type formed within the well region at the both ends of the gate electrode. When writing in the fuse element, a first writing potential is applied to the gate electrode, a first reference potential is applied to the well region, an intermediate potential is supplied to the source regions, and the intermediate potential is lower than the first writing potential and higher than the first reference potential.

公开(公告)号：US20170365503A1

公开(公告)日：2017-12-21

申请号：US15615123

申请日：2017-06-06

申请人： SAMSUNG DISPLAY CO., LTD.

发明人： JEONG DO YANG ,  BYOUNG YONG KIM ,  SEUNG-SOO RYU ,  SANG HYEON SONG ,  JUNG YUN JO ,  SEUNG-HWA HA ,  JEONG HO HWANG

IPC分类号： H01L21/70 ,  H01L27/12 ,  H01L23/532 ,  H01L23/525 ,  H01L23/522 ,  H01L49/02 ,  H01L23/29

CPC分类号： H01L21/707 ,  H01L23/293 ,  H01L23/3157 ,  H01L23/5227 ,  H01L23/5252 ,  H01L23/53238 ,  H01L24/00 ,  H01L27/12 ,  H01L49/02

摘要： An integrated circuit includes a substrate, a pad electrode disposed on the substrate, and a passivation layer disposed on the pad electrode and including an organic insulating material. The integrated circuit further includes a bump electrode disposed on the passivation layer and connected to the pad electrode through a contact hole. The passivation layer includes an insulating portion having a first thickness and covering an adjacent edge region of the pad electrode and the substrate, and a bump portion having a second thickness, that is greater than the first thickness, and covering a center portion of the pad electrode.

公开(公告)号：US20170345830A1

公开(公告)日：2017-11-30

申请号：US15674558

申请日：2017-08-11

申请人： GLOBALFOUNDRIES Singapore Pte. Ltd.

发明人： Ping ZHENG ,  Eng Huat TOH ,  Kiok Boone Elgin QUEK ,  Yuan SUN

IPC分类号： H01L27/112 ,  H01L29/06 ,  H01L29/786 ,  H01L29/66 ,  H01L29/423 ,  B82Y40/00 ,  B82Y10/00

CPC分类号： H01L27/11206 ,  B82Y10/00 ,  B82Y40/00 ,  H01L23/5252 ,  H01L29/0673 ,  H01L29/42392 ,  H01L29/66439 ,  H01L29/66545 ,  H01L29/775 ,  H01L29/7851 ,  H01L29/7853 ,  Y10S977/765 ,  Y10S977/888 ,  Y10S977/943

摘要： Devices and methods for forming a device are presented. The method includes providing a substrate prepared with at least a first region for accommodating an anti-fuse based memory cell. A fin structure is formed in the first region. The fin structure includes top and bottom fin portions and includes channel and non-channel regions defined along the length of the fin structure. An isolation layer is formed on the substrate. The isolation layer has a top isolation surface disposed below a top fin surface, leaving the top fin portion exposed. At least a portion of the exposed top fin portion in the channel region is processed to form a sharpened tip profile at top of the fin. A gate having a gate dielectric and a metal gate electrode is formed over the substrate. The gate wraps around the channel region of the fin structure.