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    Differential amplifier with gain substantially independent of temperature
    31.
    发明申请
    Differential amplifier with gain substantially independent of temperature 失效
    差分放大器，其增益基本上与温度无关

    公开(公告)号：US20030038678A1

    公开(公告)日：2003-02-27

    申请号：US10182642

    申请日：2002-09-23

    发明人： Vincent Dessard ,  Denise Flandre

    IPC分类号： H03F003/45

    CPC分类号： H03F3/4565 ,  H03F3/45183 ,  H03F3/45659 ,  H03F2203/45644 ,  H03F2203/45658 ,  H03F2203/45682

    摘要： A differential amplifier is described comprising an input branch for receiving differential and common mode input signal components; an output branch providing differential and common mode output signal components; and the differential amplifier being adapted to set a relationship between the magnitude of the common mode output signal component level of the amplifier with respect to the magnitude of the common mode input signal component level to the input stage so that the common mode output signal component level intrinsically follows the common mode input signal component level as a common mode follower without using feedback control of the common mode output signal component. Also an asymmetrical amplifier is described which may be advantageously used as a component of the differential amplifier.

    摘要翻译： 描述了差分放大器，其包括用于接收差分和共模输入信号分量的输入分支; 输出分支，提供差分和共模输出信号分量; 并且所述差分放大器适于将所述放大器的共模输出信号分量电平的大小相对于所述共模输入信号分量电平的大小相对于所述输入级之间的关系设置，使得所述共模输出信号分量电平 本质上遵循共模输入信号分量电平作为共模跟随器，而不使用共模输出信号分量的反馈控制。 还描述了可以有利地用作差分放大器的组件的非对称放大器。

    Regulated-cascode amplifier with clamping circuit
    32.
    发明授权
    Regulated-cascode amplifier with clamping circuit 有权
    具有钳位电路的调节串联放大器

    公开(公告)号：US06377120B1

    公开(公告)日：2002-04-23

    申请号：US09655005

    申请日：2000-09-05

    申请人： Chih-Cheng Hsieh

    发明人： Chih-Cheng Hsieh

    IPC分类号： H03F345

    CPC分类号： H03F3/45188 ,  H03F2203/45292 ,  H03F2203/45296 ,  H03F2203/45314 ,  H03F2203/45356 ,  H03F2203/45631 ,  H03F2203/45636 ,  H03F2203/45641 ,  H03F2203/45651 ,  H03F2203/45682

    摘要： A regulated-cascode amplifier circuit comprising a positive sub-line, a negative sub-line, a first auxiliary amplifier, a second auxiliary amplifier and a clamping circuit. The positive sub-line has a positive output terminal and the negative sub-line has a negative output terminal. The positive and negative sub-line each has a cascode transistor structure. Each auxiliary amplifier includes a positive input terminal, a negative input terminal, a positive-bias output terminal and a negative-bias output terminal. The clamping circuit includes a first diode and a second diode. The front terminal of the first diode is electrically connected to the end terminal of the second diode. The front terminal of the second diode is electrically connected to the end terminal of the first diode. In addition, each auxiliary diode is connected to a clamping circuit such that the positive-bias output terminal and the negative-bias output terminal are connected to the two terminals of the diode clamping circuit respectively.

    摘要翻译： 包括正子线，负子线，第一辅助放大器，第二辅助放大器和钳位电路的调节级共源共栅放大器电路。 正子线具有正输出端子，负子线具有负输出端子。 正和负子行各自具有共源共栅晶体管结构。 每个辅助放大器包括正输入端，负输入端，正偏置输出端和负偏压输出端。 钳位电路包括第一二极管和第二二极管。 第一二极管的前端子电连接到第二二极管的端子端子。 第二二极管的前端子电连接到第一二极管的端子端子。 此外，每个辅助二极管连接到钳位电路，使得正偏置输出端子和负偏置输出端子分别连接到二极管钳位电路的两个端子。

    Slew rate boost circuitry and method
    33.
    发明授权
    Slew rate boost circuitry and method 有权
    压摆率升压电路和方法

    公开(公告)号：US06359512B1

    公开(公告)日：2002-03-19

    申请号：US09765267

    申请日：2001-01-18

    申请人： Vadim V. Ivanov ,  Shilong Zhang ,  Gregory H. Johnson

    发明人： Vadim V. Ivanov ,  Shilong Zhang ,  Gregory H. Johnson

    IPC分类号： H03F345

    CPC分类号： H03F3/45183 ,  H03F1/3223 ,  H03F1/483 ,  H03F3/303 ,  H03F3/45192 ,  H03F2203/45682 ,  H03F2203/45702

    摘要： An operational amplifier includes a differential input stage (30) having first (2) and second (3) input conductors, a class AB output stage (20) coupled to an output of the differential input stage (30) and including a pull-up transistor (M11) having a source coupled to a first supply voltage (VDD), a drain coupled to an output conductor (17), and a gate coupled to a first terminal (14) of a class AB control circuit (11), and a pull-down transistor (M12) having a source coupled to a second supply voltage (GND), a drain coupled to the output conductor (17), and a gate coupled to a second terminal (15) of the class AB control circuit (11). A differential input signal is applied between the first (2) and second (3) input conductors, and simultaneously also is applied between first and second inputs of a first unbalanced differential amplifier (31) and between first and second input to the second unbalanced differential amplifier (32). If the differential input signal is of a first polarity and is of a magnitude substantially greater than a threshold voltage of the first unbalanced differential amplifier (31), the magnitude of a turn-on voltage of the pull-down transistor (M12) is decreased and the magnitude of a turn-on voltage of the pull-up transistor (M11) is increased in response to an output voltage produced by the first unbalanced differential amplifier (31). However, if the differential input signal is of a second polarity and is of a magnitude substantially greater than a threshold voltage of the second unbalanced differential amplifier (32), then the magnitude of a turn-on voltage of the pull-up transistor (M11) is increased and the magnitude of a turn-on voltage of the pull-down transistor (M12) is simultaneously decreased, in response to an output voltage produced by the second unbalanced differential amplifier (32).

    摘要翻译： 运算放大器包括具有第一（2）和第二（3）输入导体的差分输入级（30），耦合到差分输入级（30）的输出的AB类输出级（20）并且包括上拉 晶体管（M11）具有耦合到第一电源电压（VDD）的源极，耦合到输出导体（17）的漏极和耦合到AB类控制电路（11）的第一端子（14）的栅极，以及 具有耦合到第二电源电压（GND）的源极的下拉晶体管（M12），耦合到输出导体（17）的漏极和耦合到AB类控制电路的第二端子（15）的栅极 11）。 差分输入信号施加在第一（2）和第二（3）输入导体之间，同时也被施加在第一不平衡差分放大器（31）的第一和第二输入端之间以及在第二和第二输入端之间的第二和第二输入端 放大器（32）。 如果差分输入信号具有第一极性并且具有显着大于第一不平衡差分放大器（31）的阈值电压的幅度，则下拉晶体管（M12）的接通电压的幅度减小 并且上拉晶体管（M11）的接通电压的大小响应于由第一不平衡差分放大器（31）产生的输出电压而增加。 然而，如果差分输入信号具有第二极性并且具有显着大于第二不平衡差分放大器（32）的阈值电压的幅度，则上拉晶体管（M11）的接通电压的幅度 ）并且响应于由第二不平衡差分放大器（32）产生的输出电压同时降低下拉晶体管（M12）的接通电压的幅度。

    Differential current mode output circuit for electro-optical sensor arrays
    34.
    发明授权
    Differential current mode output circuit for electro-optical sensor arrays 有权
    差分电流模式输出电路用于电光传感器阵列

    公开(公告)号：US06344651B1

    公开(公告)日：2002-02-05

    申请号：US09427645

    申请日：1999-10-27

    申请人： James T. Woolaway ,  William J. Parrish ,  Stephen H. Black

    发明人： James T. Woolaway ,  William J. Parrish ,  Stephen H. Black

    IPC分类号： H03F345

    CPC分类号： G01J5/24 ,  H03F3/082 ,  H03F3/45197 ,  H03F3/68 ,  H03F2203/45652 ,  H03F2203/45658 ,  H03F2203/45682 ,  H04N5/33

    摘要： A differential current mode amplifier circuit (5,5′) includes a first circuit leg having a first current source providing a current I1 coupled in series with a first transistor (m1) at a first circuit node (n1). The first transistor has a control terminal for coupling to an input signal potential (Vs). Vs is obtained from a unit cell of a radiation detector array, and is indicative of a magnitude of an integrated, photon-induced charge. The first circuit leg outputs a first output current (Is). A second circuit leg includes a second current source providing a current I2 coupled in series with a second transistor (m2) at a second circuit node (n2). The second transistor has a control terminal for coupling to an input reference potential (Vr). The second circuit leg outputs a second output current (Ir). A resistance (Rs) is coupled between the first circuit leg and the second circuit leg at the first circuit node and the second node. The current flow through Rs is proportional to a difference between Vs and Vr, and is thus indicative of a magnitude of Vs.

    摘要翻译： 差分电流模式放大器电路（5,5'）包括具有第一电流源的第一电路支路，该第一电流源提供与第一电路节点（n1）上的第一晶体管（m1）串联耦合的电流I1。 第一晶体管具有用于耦合到输入信号电位（Vs）的控制端子。 Vs是从放射线检测器阵列的单位单元获得的，并且表示积分的光子诱导电荷的大小。 第一电路支路输出第一输出电流（Is）。 第二电路支路包括提供与第二电路节点（n2）上的第二晶体管（m2）串联耦合的电流I2的第二电流源。 第二晶体管具有用于耦合到输入参考电位（Vr）的控制端子。 第二电路支路输出第二输出电流（Ir）。 电阻（Rs）在第一电路节点和第二节点处耦合在第一电路支路和第二电路支路之间。 通过Rs的电流与Vs和Vr之间的差成比例，因此表示Vs的大小。

    Multi-stage high-gain high-speed amplifier
    35.
    发明授权
    Multi-stage high-gain high-speed amplifier 失效
    多级高增益高速放大器

    公开(公告)号：US5847600A

    公开(公告)日：1998-12-08

    申请号：US638287

    申请日：1996-04-26

    申请人： Todd L. Brooks ,  Lawrence Singer

    发明人： Todd L. Brooks ,  Lawrence Singer

    IPC分类号： H03F3/00 ,  H03F3/45 ,  H03F3/72

    CPC分类号： H03F3/4521 ,  H03F3/005 ,  H03F3/45188 ,  H03F3/45242 ,  H03F3/72 ,  H03F2203/45356 ,  H03F2203/45644 ,  H03F2203/45651 ,  H03F2203/45682

    摘要： A two-stage switched-capacitor residue amplifier having novel circuitry in the first and second stages provides fast and accurate settling while configured with a large closed-loop gain, and also provides low power consumption while powered from a five volt supply. The invention is particularly well suited for use in a multi-stage, pipe-lined analog-to-digital converter (ADC) that converts multiple bits in the first pipeline stage. Complementary PMOS and NMOS differential pairs are used in the first and/or second stage to increase the current slew capability of the amplifier. Current mirror gain and/or positive feedback is used in the second stage to increase transonductance and bandwidth. Cascode transistors are used in the output of the first and/or second stages and active cascode gain enhancement is used in the first stage to increase dc gain and accuracy. The common mode level at the output of the second stage is controlled by injecting a pair of control currents (representative of the difference between a common-mode level actually at the output of the second stage and a desired common mode level) into a pair of mirror input nodes in the second stage. The common mode level of the first stage is controlled from a common node of a differential pair of the second stage. The two-stage amplifier of the invention provides a gain bandwidth product of 800 MHz, a closed-loop bandwidth of 50 MHz, a dc gain 90 dB, and a power consumption 80 mW.

    摘要翻译： 在第一和第二阶段具有新颖电路的两级开关电容器残余放大器提供快速和准确的稳定，同时配置有大的闭环增益，并且在由五伏电源供电时也提供低功耗。 本发明特别适用于在第一流水线级中转换多个比特的多级管线模数转换器（ADC）。 互补PMOS和NMOS差分对用于第一和/或第二级以增加放大器的电流转换能力。 在第二阶段使用电流镜增益和/或正反馈来增加电导率和带宽。 串级晶体管用于第一级和/或第二级的输出，并且在第一级中使用有源共源共轭增益增强以增加直流增益和精度。 第二级输出端的共模电平通过将一对控制电流（代表第二级输出端的共模电平与期望的共模电平之间的差）代入一对 第二阶段的镜像输入节点。 第一级的共模级由第二级的差分对的公共节点控制。 本发明的两级放大器提供800MHz的增益带宽乘积，50MHz的闭环带宽，直流增益90dB，功耗80mW。

    Fully differential high gain cascode amplifier
    36.
    发明授权
    Fully differential high gain cascode amplifier 失效
    全差分高增益共源共栅放大器

    公开(公告)号：US5748040A

    公开(公告)日：1998-05-05

    申请号：US749383

    申请日：1996-11-06

    申请人： Ka Yin Leung

    发明人： Ka Yin Leung

    IPC分类号： H03F3/45

    CPC分类号： H03F3/45192 ,  H03F3/45659 ,  H03F2203/45356 ,  H03F2203/45682

    摘要： A very high gain cascode amplifier includes a cascoded differential structure wherein a cascoded N-channel leg comprised of two series connected transistors (56) and (58) are connected between an output node (30) and ground with a corresponding P-channel cascode leg comprised of series connected P-channel transistors (38) and (40) connected between node (30) and V.sub.DD. Transistor (58) is connected to bias voltage, with transistor (56) having a gate thereof connected to a bias circuit (72) which provides gain thereto to increase the gain of a cascoded leg while not introducing any error into the amplifier. The bias circuit (72) has an imbedded structure that sets the gate voltage of transistor (56) to a voltage equal to one threshold voltage plus twice the V.sub.on voltage of transistors (56) and (58). This is achieved via negative feedback with transistors that track any errors, such that all errors are cancelled out and the maximum voltage swing is maintained for all operational characteristics of the cascoded leg.

    摘要翻译： 非常高的增益共源共栅放大器包括级联差分结构，其中由两个串联连接的晶体管（56）和（58）组成的级联N沟道支路连接在输出节点（30）和地之间，并与相应的P沟道共源共享支路 包括连接在节点（30）和VDD之间的串联连接的P沟道晶体管（38）和（40）。 晶体管（58）连接到偏置电压，晶体管（56）的栅极连接到偏置电路（72），偏置电路（72）提供增益，以增加级联支路的增益，同时不向放大器引入任何误差。 偏置电路（72）具有嵌入式结构，其将晶体管（56）的栅极电压设置为等于一个阈值电压加上晶体管（56）和（58）的Von电压的两倍的电压。 这是通过负反馈来实现的，晶体管跟踪任何误差，使得所有误差被抵消，并且对于共享的腿的所有操作特性都保持最大电压摆幅。

    Amplifier circuit and method
    40.
    发明授权
    Amplifier circuit and method 有权
    放大器电路及方法

    公开(公告)号：US08698559B2

    公开(公告)日：2014-04-15

    申请号：US13402907

    申请日：2012-02-23

    申请人： Sunil Kasanyal

    发明人： Sunil Kasanyal

    IPC分类号： H03F3/45

    CPC分类号： H03F3/45192 ,  H03F3/45632 ,  H03F2200/408 ,  H03F2200/516 ,  H03F2203/45101 ,  H03F2203/45244 ,  H03F2203/45482 ,  H03F2203/45652 ,  H03F2203/45682 ,  H03F2203/45702 ,  H03K5/003 ,  H04L25/0292

    摘要： A differential amplifier circuit comprises a differential pre-amplifying stage which is designed to allow an input signal with a first common mode voltage range, and to generate an output which has a narrower common mode voltage variation. This pre-amplifier stage is designed to accept a large common mode input voltage and to process the signal so that it can be amplified by a main amplifying stage which is designed to allow an input signal with a smaller common mode voltage range.

    摘要翻译： 差分放大器电路包括差分预放大级，其被设计为允许具有第一共模电压范围的输入信号，并且产生具有较窄共模电压变化的输出。 该前置放大器级被设计为接受大的共模输入电压并处理信号，使得其可以被主放大级放大，该主放大级被设计为允许具有较小共模电压范围的输入信号。