公开(公告)号：US20150249051A1

公开(公告)日：2015-09-03

申请号：US14712940

申请日：2015-05-15

Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.

Inventor： Ming Hsien TSAI ,  Hsieh-Hung HSIEH ,  Tzu-Jin YEH ,  Chewn-Pu JOU ,  Sa-Lly LIU ,  Fu-Lung HSUEH

IPC: H01L23/522 ,  H03F1/26 ,  H01L23/58 ,  H03F3/04 ,  H01L27/06 ,  H01L49/02

CPC classification number: H01L23/5226 ,  H01L23/481 ,  H01L23/5225 ,  H01L23/5227 ,  H01L23/5384 ,  H01L23/585 ,  H01L23/645 ,  H01L25/0657 ,  H01L27/0688 ,  H01L27/0705 ,  H01L27/092 ,  H01L28/10 ,  H01L2225/06527 ,  H01L2225/06537 ,  H01L2225/06544 ,  H01L2924/0002 ,  H03F1/26 ,  H03F3/04 ,  H03F2200/294 ,  H03F2200/372 ,  H01L2924/00

Abstract: The three dimensional (3D) circuit includes a first tier including a semiconductor substrate, a second tier disposed adjacent to the first tier, a three dimensional inductor including an inductive element portion, the inductive element portion including a conductive via extending from the first tier to a dielectric layer of the second tier. The 3D circuit includes a ground shield surrounding at least a portion of the conductive via. In some embodiments, the ground shield includes a hollow cylindrical cage. In some embodiments, the 3D circuit is a low noise amplifier.

Abstract translation: 三维（3D）电路包括包括半导体衬底的第一层，与第一层相邻设置的第二层，包括电感元件部分的三维电感器，电感元件部分包括从第一层延伸到 第二层的介电层。 3D电路包括围绕导电通孔的至少一部分的接地屏蔽。 在一些实施例中，接地屏蔽包括中空圆柱形笼。 在一些实施例中，3D电路是低噪声放大器。

公开(公告)号：US09112452B1

公开(公告)日：2015-08-18

申请号：US12836307

申请日：2010-07-14

Applicant: Nadim Khlat

Inventor： Nadim Khlat

IPC: H03G3/00 ,  H03F3/04

CPC classification number: H03F3/04 ,  H03F1/0227 ,  H03G3/00

Abstract: The present disclosure relates to power supply circuitry that has wide bandwidth and achieves high efficiency by using at least one energy storage element for efficient power transfer between two power supply circuits and to an amplitude modulated load. Specifically, the power supply circuitry may include a first power supply circuit, which may be a switching power supply circuit, a second power supply circuit, which may be a linear power supply circuit and may include the energy storage element, and control circuitry to facilitate efficient power transfer. The control circuitry may select one of multiple operating modes, which may include a first operating mode, during which the first power supply circuit may provide power to the energy storage element, and a second operating mode, during which the second power supply circuit may provide power to the amplitude modulated load from the energy storage element.

Abstract translation: 本公开涉及通过使用至少一个能量存储元件在两个电源电路和幅度调制负载之间进行有效功率传输而具有宽带宽并且实现高效率的电源电路。 具体地，电源电路可以包括第一电源电路，其可以是开关电源电路，第二电源电路，其可以是线性电源电路，并且可以包括能量存储元件，以及便于控制的电路 高效的电力转移。 控制电路可以选择多种操作模式中的一种，其可以包括第一操作模式，其中第一电源电路可以向能量存储元件提供电力;以及第二操作模式，在第二操作模式期间，第二电源电路可以提供 来自能量存储元件的幅度调制负载的功率。

公开(公告)号：US20150222286A1

公开(公告)日：2015-08-06

申请号：US14173595

申请日：2014-02-05

Applicant: Innophase, Inc.

Inventor： Xuejun Zhang ,  Yang Xu

IPC: H03M1/00 ,  G05F1/625 ,  H03M3/00 ,  H03F3/04 ,  H03M1/08

CPC classification number: H03M3/50 ,  G05F1/625 ,  G05F3/262 ,  H03F3/04 ,  H03M1/00 ,  H03M1/002 ,  H03M1/0854 ,  H03M1/742 ,  H03M1/747

Abstract: A DAC using current mirrors suitable for use in a modulator. Embodiments include a current-generating circuit to provide an information signal; a bias current source; a current mirror having a mirror input transistor connected to the current generating circuit and the bias current source, and being driven by the bias current and the varying current signal and having a corresponding varying voltage signal at a control terminal; a signal shaping filter interposed between the mirror input transistor and an output mirror transistor configured to limit a bandwidth of the varying voltage signal; the output mirror transistor configured to generate a band-limited varying current signal and a mirrored bias current; and, a mirrored bias current reduction circuit connected to the output mirror transistor configured to reduce the mirrored bias current.

Abstract translation: 使用适合用于调制器的电流镜的DAC。 实施例包括提供信息信号的电流产生电路; 偏置电流源; 电流镜，其具有连接到电流产生电路和偏置电流源的反射镜输入晶体管，并由偏置电流和变化的电流信号驱动，并且在控制端处具有相应的变化电压信号; 插入在所述反射镜输入晶体管和被配置为限制所述变化的电压信号的带宽的输出镜像晶体管之间的信号整形滤波器; 所述输出镜晶体管被配置为产生带限变化电流信号和镜像偏置电流; 以及连接到输出镜晶体管的镜像偏置电流降低电路，被配置为减少镜像偏置电流。

公开(公告)号：US09075486B2

公开(公告)日：2015-07-07

申请号：US13316273

申请日：2011-12-09

Applicant: Chun-Chung Huang ,  I-Shu Lee ,  Shih-Yuan Hsu ,  Te-Sheng Chiu

Inventor： Chun-Chung Huang ,  I-Shu Lee ,  Shih-Yuan Hsu ,  Te-Sheng Chiu

IPC: G01R27/26 ,  G06F3/041 ,  G06F3/045 ,  G06F3/044 ,  G01D5/24

CPC classification number: G01R27/2605 ,  G01D5/24 ,  G01R1/30 ,  G06F3/044 ,  H03F3/04 ,  H03F2200/474

Abstract: A transconductance amplifier mirror circuit is connected to an electrode for sensing the capacitance of the electrode with reference to ground, or the capacitance between the electrode and another electrode. A voltage level change is produced on the electrode connected to the transconductance amplifier mirror circuit to cause the transconductance amplifier mirror circuit to supply charges to or drain charges from a charge calculation circuit. The charge amount variation is converted to a signal for calculating the sensed capacitance.

Abstract translation: 跨导放大器镜电路连接到电极，用于相对于接地或电极与另一电极之间的电容感测电极的电容。 在连接到跨导放大器反射镜电路的电极上产生电压电平变化，以使跨导放大器反射镜电路向电荷计算电路提供电荷或从电荷计算电路漏出电荷。 电荷量变化被转换为用于计算感测电容的信号。

公开(公告)号：US20140266962A1

公开(公告)日：2014-09-18

申请号：US14213897

申请日：2014-03-14

Applicant: DockOn AG

Inventor： Alexandre Dupuy ,  Forrest Brown ,  Patrick Rada

IPC: H01Q21/00 ,  H01Q7/00 ,  H01P5/19

CPC classification number: H01P5/19 ,  H01Q7/00 ,  H01Q21/0075 ,  H03D1/08 ,  H03D1/18 ,  H03D7/02 ,  H03D7/12 ,  H03D7/165 ,  H03D7/166 ,  H03D11/04 ,  H03D11/08 ,  H03D2200/0043 ,  H03D2200/0098 ,  H03F1/08 ,  H03F3/04 ,  H03F3/191 ,  H03F2200/165 ,  H03F2200/294 ,  H03G11/04

Abstract: An N-way radio frequency (RF) divider/combiner is formed as a combination including an input port electrically coupled to a first 2-way divider/combiner and a second 2-way divider/combiner. An antenna may be coupled to at least one port of the N-way divider. The antenna may be formed as a compound printed loop (CPL) antenna. The N-way RF divider/combiner may be configured to provide N inputs and M output ports, wherein N and M are integers and any of the M output ports and N input ports can be connected to any combinations of devices. Such devices may include, e.g., an antenna including but not limited to a CPL antenna, RF receive port, transmit port, amplifier, RF switch, low noise amplifier (LNA), oscillator, tuning circuit, matching circuit, lumped element circuit, active circuit, diode, adjustable inductive circuit, and adjustable capacitive circuit.

Abstract translation: 形成N路射频（RF）分频器/组合器作为组合，其包括电耦合到第一2路分频器/组合器和第二2路分频器/组合器的输入端口。 天线可以耦合到N路分频器的至少一个端口。 天线可以形成为复合印刷环（CPL）天线。 N路RF分频器/组合器可以被配置为提供N个输入和M个输出端口，其中N和M是整数，并且M个输出端口和N个输入端口中的任一个可以连接到设备的任何组合。 这样的设备可以包括例如包括但不限于CPL天线，RF接收端口，发射端口，放大器，RF开关，低噪声放大器（LNA），振荡器，调谐电路，匹配电路，集总元件电路，有源 电路，二极管，可调电感电路和可调容性电路。

公开(公告)号：US20140240050A1

公开(公告)日：2014-08-28

申请号：US14173207

申请日：2014-02-05

Applicant: KABUSHIKI KAISHA TOSHIBA

Inventor： Kan SHIMIZU

IPC: H03F1/02

CPC classification number: G05F3/242 ,  H03F1/0211 ,  H03F3/04

Abstract: A power circuit includes a bridge circuit connected to a first node by which an output voltage is supplied to a load circuit including an amplifier containing a CMOS inverter, and configured to generate a current flowing in a first current channel and a current flowing in a second current channel in accordance with a voltage difference between the output voltage and a predetermined set voltage to be supplied to the load circuit, and a current amplifier configured to generate a current flowing in a third current channel to the load circuit in accordance with an input source voltage and a difference between the current flowing in the first current channel and the current flowing in the second current channel. The predetermined set voltage that is supplied to the load circuit achieves the smallest transconductance during normal operation of the amplifier.

Abstract translation: 电源电路包括连接到第一节点的桥接电路，通过该桥接电路将输出电压提供给包括具有CMOS反相器的放大器的负载电路，并且被配置为产生在第一电流通道中流动的电流和在第二节点中流动的电流 电流通道，其根据输出电压和要提供给负载电路的预定设定电压之间的电压差;以及电流放大器，被配置为根据输入源产生在第三电流通道中流向负载电路的电流 电压和在第一电流通道中流动的电流与在第二电流通道中流动的电流之间的差。 提供给负载电路的预定设定电压在放大器的正常操作期间实现最小的跨导。

公开(公告)号：US20140159808A1

公开(公告)日：2014-06-12

申请号：US13710605

申请日：2012-12-11

Applicant: Igor Acimovic ,  Brian Racey

Inventor： Igor Acimovic ,  Brian Racey

IPC: G01R27/02 ,  G06F17/50 ,  H03F3/04

CPC classification number: G01R27/02 ,  G06F17/5036 ,  G06F17/5072 ,  H03F1/0288 ,  H03F1/56 ,  H03F3/04 ,  H03F3/191 ,  H03F3/211 ,  H03F3/245 ,  H03F2200/222 ,  H03F2200/387

Abstract: An analysis technique for (Doherty) amplifiers having a main amplifier branch and at least one peak amplifier branch. For a given input power level and assumed amplifier impedance levels, an output power level and phase response are obtained for each active device using appropriate load-pull data based on the impedance levels. The performance of the amplifier is analyzed based on the impedance levels, output power levels, and phase responses to generate updated impedance levels. The analysis is repeated until the updated impedance levels converge on steady state values. The analysis can be repeated for different input power levels. Main and peak output matching networks for the amplifier can be designed by iteratively adjusting impedance levels for the networks using appropriate load-pull contours. For the design and analysis phases, the load-pull contours include Class-AB data for the main amplifier device and Class-C data for the peak amplifier device.

Abstract translation: （Doherty）放大器的分析技术，其具有主放大器分支和至少一个峰值放大器分支。 对于给定的输入功率电平和假设的放大器阻抗电平，使用基于阻抗电平的合适的负载牵引数据为每个有源器件获得输出功率电平和相位响应。 基于阻抗水平，输出功率电平和相位响应来分析放大器的性能，以产生更新的阻抗水平。 重复分析直到更新的阻抗水平收敛于稳态值。 可以针对不同的输入功率电平重复分析。 用于放大器的主要和峰值输出匹配网络可以通过使用适当的负载拉动轮廓迭代地调整网络的阻抗水平来设计。 对于设计和分析阶段，负载拉线轮廓包括主放大器装置的AB类数据和峰值放大器装置的C类数据。

公开(公告)号：US20140097905A1

公开(公告)日：2014-04-10

申请号：US14105130

申请日：2013-12-12

Applicant: QUALCOMM INCORPORATED

Inventor： Yang XU ,  Timothy Paul PALS ,  Kevin Hsi Huai WANG

IPC: H03F3/04

CPC classification number: H03F3/04 ,  G01S19/21 ,  G01S19/34 ,  G01S19/36 ,  H03F1/02 ,  H03F1/223 ,  H03F1/3205 ,  H03F3/19 ,  H03F3/24 ,  H04B7/18513 ,  H04B2001/045 ,  Y02D70/1222 ,  Y02D70/142 ,  Y02D70/144 ,  Y02D70/146 ,  Y02D70/164 ,  Y02D70/446

Abstract: A device includes a low noise amplifier (LNA) for amplifying an input signal, with the LNA including a first transistor configured to receive the input signal, a second transistor configured to receive a bias current and forming a current mirror for the first transistor, and an operational amplifier (op amp) operative to generate a bias voltage for the first and second transistors to match operating points of the first and second transistors.

Abstract translation: 一种器件包括用于放大输入信号的低噪声放大器（LNA），其中LNA包括被配置为接收输入信号的第一晶体管，被配置为接收偏置电流并形成用于第一晶体管的电流镜的第二晶体管，以及 运算放大器（op amp），用于产生第一和第二晶体管的偏置电压以匹配第一和第二晶体管的工作点。

公开(公告)号：US20130127546A1

公开(公告)日：2013-05-23

申请号：US13741592

申请日：2013-01-15

Applicant: QUALCOMM Incorporated

Inventor： Thomas Domenick Marra ,  Aristotele Hadjichristos

IPC: H03F1/30

CPC classification number: H03F1/301 ,  H03F1/30 ,  H03F3/04 ,  H03F3/189

Abstract: Techniques for monitoring and controlling bias current of amplifiers are described. In an exemplary design, an apparatus may include an amplifier and a bias circuit. The amplifier may include at least one transistor coupled to an inductor. The bias circuit may generate at least one bias voltage for the at least one transistor in the amplifier to obtain a target bias current for the amplifier. The bias circuit may generate the at least one bias voltage based on a voltage across the inductor in the amplifier, or a current through a current mirror formed with one of the at least one transistor in the amplifier, or a gate-to-source voltage of one of the at least one transistor in the amplifier, or a voltage in a replica circuit replicating the amplifier, or a current applied to the amplifier with a switched mode power supply disabled.

公开(公告)号：US20120176200A1

公开(公告)日：2012-07-12

申请号：US13194845

申请日：2011-07-29

Applicant: Seyed-Ali Hajimiri ,  Scott D. Kee ,  Ichiri Aoki

Inventor： Seyed-Ali Hajimiri ,  Scott D. Kee ,  Ichiri Aoki

IPC: H03F3/04

CPC classification number: H03F1/0211 ,  H03F3/04 ,  H03F3/191 ,  H03F3/217 ,  H03F3/2176 ,  H03F3/45475 ,  H03F3/605 ,  H03F3/68 ,  H03F2200/507 ,  H03F2200/537 ,  H03F2200/541 ,  H03F2203/45464 ,  H03F2203/45704 ,  H03F2203/45731

Abstract: A cross-differential amplifier is provided. The cross-differential amplifier includes an inductor connected to a direct current power source at a first terminal. A first and second switch, such as transistors, are connected to the inductor at a second terminal. A first and second amplifier are connected at their supply terminals to the first and second switch. The first and second switches are operated to commutate the inductor between the amplifiers so as to provide an amplified signal while limiting the ripple voltage on the inductor and thus limiting the maximum voltage imposed across the amplifiers and switches.

Abstract translation: 提供了一个交叉差分放大器。 交叉差分放大器包括在第一端子处连接到直流电源的电感器。 诸如晶体管的第一和第二开关在第二端子连接到电感器。 第一和第二放大器在其电源端连接到第一和第二开关。 第一和第二开关被操作以在放大器之间换向电感器，以便提供放大的信号，同时限制电感器上的纹波电压，从而限制放大器和开关上施加的最大电压。