公开(公告)号：US20140203854A1

公开(公告)日：2014-07-24

申请号：US14157877

申请日：2014-01-17

申请人： Industry-Academic Cooperation Foundation, Yonsei University

发明人： Seong-Ook Jung ,  Dong-Hoon Jung ,  Kyungho Ryu ,  Jung-Hyun Park

IPC分类号： H03L7/08

CPC分类号： H03L7/0802 ,  H03L7/0814 ,  H03L7/0818 ,  H03L7/087 ,  H03L7/0995 ,  H03L7/16

摘要： Provided is a delay locked loop (DLL) including a ring oscillator (RO) including a delay line to delay a reference clock signal and generate a delayed clock signal, wherein the RO circulates, through the delay line, a feedback clock signal corresponding to the delayed clock signal to synchronize N cycles of the feedback clock signal with a cycle of the reference clock signal (where N is an integer number equal to or larger than 2); and a first frequency divider dividing the frequency of the delayed clock signal by 1/N (where N is an integer number equal to or larger than 2) to generate an output clock signal.

摘要翻译： 提供了一种包括环路振荡器（RO）的延迟锁定环路（DLL），该环路振荡器（RO）包括用于延迟参考时钟信号并产生延迟的时钟信号的延迟线，其中RO通过延迟线循环与 延迟时钟信号以使反馈时钟信号的N个周期与参考时钟信号（其中N是等于或大于2的整数）的周期同步; 以及将延迟时钟信号的频率除以1 / N（其中N是等于或大于2的整数）的第一分频器，以产生输出时钟信号。

公开(公告)号：US20140119133A1

公开(公告)日：2014-05-01

申请号：US14150563

申请日：2014-01-08

申请人： Micron Technology, Inc.

发明人： Aaron Willey ,  Yantao Ma

IPC分类号： G11C11/4076

CPC分类号： G11C11/4076 ,  G11C7/222 ,  H03K5/1565 ,  H03L7/08 ,  H03L7/0816 ,  H03L7/0818

摘要： Memories, clock generators and methods for providing an output clock signal are disclosed. One such method includes delaying a buffered clock signal by an adjustable delay to provide an output clock signal, providing a feedback clock signal from the output clock signal, and adjusting a duty cycle of the buffered clock signal based at least in part on the feedback clock signal. An example clock generator includes a forward clock path configured to provide a delayed output clock signal from a clock driver circuit, and further includes a feedback clock path configured to provide a feedback clock signal based at least in part on the delayed output clock signal, for example, frequency dividing the delayed output clock signal. The feedback clock path further configured to control adjustment a duty cycle of the buffered input clock signal based at least in part on the feedback clock signal.

摘要翻译： 公开了用于提供输出时钟信号的存储器，时钟发生器和方法。 一种这样的方法包括将缓冲的时钟信号延迟可调延迟以提供输出时钟信号，从输出时钟信号提供反馈时钟信号，以及至少部分地基于反馈时钟调整缓冲时钟信号的占空比 信号。 示例时钟发生器包括正向时钟路径，其构造成从时钟驱动器电路提供延迟的输出时钟信号，并且还包括被配置为至少部分地基于延迟的输出时钟信号来提供反馈时钟信号的反馈时钟路径，用于 例如，对延迟输出时钟信号进行分频。 反馈时钟路径还被配置为至少部分地基于反馈时钟信号来控制缓冲的输入时钟信号的占空比调节。

公开(公告)号：US20140002149A1

公开(公告)日：2014-01-02

申请号：US13711692

申请日：2012-12-12

申请人： SK HYNIX INC.

发明人： Jae Min JANG ,  Yong Ju KIM ,  Dae Han KWON ,  Hae Rang CHOI

IPC分类号： H03H11/26 ,  H03L7/06

CPC分类号： H03H11/265 ,  H03L7/06 ,  H03L7/0814 ,  H03L7/0816 ,  H03L7/0818 ,  H03L7/085

摘要： A clock generation circuit includes a delay line, a delay modeling block, a phase detection block, a multi-update signal generation block, and a delay line. The delay line delays an input clock and generates a delayed clock. The delay modeling block delays the delayed clock by a modeled delay value and generates a feedback clock. The phase detection block compares phases of the input clock and the feedback clock and generates phase information, and quantizes a phase difference between the input clock and the feedback clock and generates phase codes. The multi-update signal generation block generates a multi-update signal in response to the phase codes. The delay line control block changes a delay amount of the delay line in response to the multi-update signal and the phase information.

摘要翻译： 时钟生成电路包括延迟线，延迟建模块，相位检测块，多更新信号生成块和延迟线。 延迟线延迟输入时钟并产生延迟时钟。 延迟建模块通过建模延迟值将延迟时钟延迟并产生反馈时钟。 相位检测块比较输入时钟和反馈时钟的相位，并产生相位信息，并量化输入时钟和反馈时钟之间的相位差，并产生相位代码。 多更新信号生成块响应于相位代码生成多更新信号。 响应于多更新信号和相位信息，延迟线控制块改变延迟线的延迟量。

公开(公告)号：US08564345B2

公开(公告)日：2013-10-22

申请号：US13078609

申请日：2011-04-01

申请人： Wing K. Yu

发明人： Wing K. Yu

IPC分类号： H03L7/06

CPC分类号： H03L7/0818

摘要： Digitally controllable delay lines including fine grain and coarse grain delay elements, and methods and system to calibrate the delay lines in fine grain increments. Calibration may include calibrating a number of fine grain elements for which a combined delay is substantially equal to a delay of a coarse grain element, and calibrating numbers of fine grain and coarse grain elements which a combined delay corresponds to a period of a reference clock. A digitally controlled delay line may be implemented as part of a digital delay locked loop (DLL), and calibration parameters may be provided to a slave DLL having a similarly implemented delay line. A digitally controllable DLL may provide relatively low-power, high-resolution over a spectrum of process, voltage, and temperature variations, and may be implemented in relatively high-speed applications previously reserved for analog DLLs.

摘要翻译： 数字可控延迟线，包括细晶粒和粗粒延迟元件，以及以细晶粒增量校准延迟线的方法和系统。 校准可以包括校准多个细晶粒元素，其中组合延迟基本上等于粗晶粒元素的延迟，以及校准细晶粒和粗晶粒元素的数目，合并延迟对应于参考时钟的周期。 数字控制的延迟线可以被实现为数字延迟锁定环（DLL）的一部分，并且校准参数可以被提供给具有类似实现的延迟线的从动DLL。 数字可控DLL可以在过程，电压和温度变化的频谱上提供相对低功率，高分辨率，并且可以在先前为模拟DLL保留的相对高速的应用中实现。

公开(公告)号：US20130265090A1

公开(公告)日：2013-10-10

申请号：US13443856

申请日：2012-04-10

申请人： Yantao Ma

发明人： Yantao Ma

IPC分类号： H03L7/00 ,  H03K3/027 ,  H03K3/00

CPC分类号： H03K19/00346 ,  G11C7/1009 ,  G11C7/222 ,  H03K3/0375 ,  H03L7/0814 ,  H03L7/0816 ,  H03L7/0818

摘要： Apparatuses, circuits, and methods are disclosed for reducing or eliminating unintended operation resulting from metastability in data synchronization. In one such example apparatus, a sampling circuit is configured to provide four samples of a data input signal. A first and a second of the four samples are associated with a first edge of a latching signal, and a third and a fourth of the four samples are associated with a second edge of the latching signal. A masking circuit is configured to selectively mask a signal corresponding to one of the four samples responsive to the four samples not sharing a common logic level. The masking circuit is also configured to provide a decision signal responsive to selectively masking or not masking the signal.

摘要翻译： 公开了用于减少或消除由数据同步中的亚稳态导致的非预期操作的装置，电路和方法。 在一个这样的示例性装置中，采样电路被配置为提供数据输入信号的四个采样。 四个样本中的第一和第二样本与锁存信号的第一边缘相关联，并且四个样本中的第三和第四个与锁存信号的第二边缘相关联。 屏蔽电路被配置为响应于不共享公共逻辑电平的四个采样来选择性地屏蔽对应于四个采样中的一个采样的信号。 屏蔽电路还被配置为响应于选择性地屏蔽或不掩蔽信号来提供决定信号。

公开(公告)号：US08547153B2

公开(公告)日：2013-10-01

申请号：US13679045

申请日：2012-11-16

申请人： Industry-Academic Cooperation Foundation, Yonsei University

发明人： Seongook Jung ,  Jung-Hyun Park ,  Kyung Ho Ryu ,  Dong Hun Jung

IPC分类号： H03L7/06

CPC分类号： H03L7/00 ,  H03L7/0816 ,  H03L7/0818 ,  H03L7/087

摘要： A delay locked loop in accordance with some embodiments of the inventive concept may include a delay signal generation part generating a first delay signal having a first phase and a second delay signal having a second phase by delaying a reference signal on the basis of a delay control signal; a phase synthesizing part generating at least one third signal having a third phase using the first delay signal and the second delay signal; and a phase detection part generating a control code by comparing the reference signal with each of the first delay signal, the second delay signal and the third signal.

摘要翻译： 根据本发明构思的一些实施例的延迟锁定环可以包括延迟信号生成部分，其通过基于延迟控制来延迟参考信号来生成具有第一相位的第一延迟信号和具有第二相位的第二延迟信号 信号; 使用第一延迟信号和第二延迟信号产生具有第三相的至少一个第三信号的相位合成部分; 以及相位检测部分，通过将参考信号与第一延迟信号，第二延迟信号和第三信号中的每一个进行比较来产生控制码。

公开(公告)号：US08519759B2

公开(公告)日：2013-08-27

申请号：US13190004

申请日：2011-07-25

申请人： Young Suk Seo

发明人： Young Suk Seo

IPC分类号： H03L7/06

CPC分类号： H03L7/0818 ,  H03L7/0814 ,  H03L7/0816 ,  H03L7/087 ,  H03L7/10

摘要： A synchronization circuit includes a measurement unit configured to measure a difference between an initial delay amount of an input clock signal and an initial delay amount of a feedback clock signal and generate a phase difference detection signal, an initial delay time setting unit configured to generate an initial delay time setting signal in response to the phase difference detection signal, a shift register configured to generate a shift signal in response to the initial delay time setting signal, and a delay chain having an initial delay time set in response to the shift signal.

摘要翻译： 同步电路包括：测量单元，被配置为测量输入时钟信号的初始延迟量与反馈时钟信号的初始延迟量之间的差异，并产生相位差检测信号;初始延迟时间设置单元， 响应于所述相位差检测信号的初始延迟时间设定信号，被配置为响应于所述初始延迟时间设置信号产生移位信号的移位寄存器，以及响应于所述移位信号设置的初始延迟时间的延迟链。

公开(公告)号：US08502579B2

公开(公告)日：2013-08-06

申请号：US13734745

申请日：2013-01-04

申请人： Micron Technology, Inc.

发明人： Tyler J. Gomm

IPC分类号： H03L7/06

CPC分类号： H03L7/0818 ,  H03K5/133 ,  H03K5/14 ,  H03L7/0814 ,  H03L7/089

摘要： Locked loops, delay lines, delay circuits, and methods for delaying signals are disclosed. An example delay circuit includes a delay line including a plurality of delay stages, each delay stage having an input and further having a single inverting delay device, and also includes a two-phase exit tree coupled to the delay line and configured to provide first and second output clock signals responsive to clock signals from inputs of the delay stages of the plurality of delay stages. Another example delay circuit includes a delay line configured to provide a plurality of delayed clock signals, each of the delayed clock signals having a delay relative to a previous delayed clock signal equal to a delay of a single inverting delay device. The example delay circuit also includes a two-phase exit tree configured to provide first and second output clock signals responsive to the delayed clock signals.

公开(公告)号：US08461889B2

公开(公告)日：2013-06-11

申请号：US12757597

申请日：2010-04-09

申请人： Aaron Willey ,  Yantao Ma

发明人： Aaron Willey ,  Yantao Ma

IPC分类号： H03L7/06

CPC分类号： G11C11/4076 ,  G11C7/222 ,  H03K5/1565 ,  H03L7/08 ,  H03L7/0816 ,  H03L7/0818

摘要： Memories, clock generators and methods for providing an output clock signal are disclosed. One such method includes delaying a buffered clock signal by a adjustable delay to provide an output clock signal, providing a feedback clock signal from the output clock signal, and adjusting a duty cycle of the buffered clock signal based at least in part on the feedback clock signal. An example clock generator includes a forward clock path configured to provide a delayed output clock signal from a clock driver circuit, and further includes a feedback clock path configured to provide a feedback clock signal based at least in part on the delayed output clock signal, for example, frequency dividing the delayed output clock signal. The feedback clock path further configured to control adjustment a duty cycle of the buffered input clock signal based at least in part on the feedback clock signal.

摘要翻译： 公开了用于提供输出时钟信号的存储器，时钟发生器和方法。 一种这样的方法包括将缓冲的时钟信号延迟可调延迟以提供输出时钟信号，从输出时钟信号提供反馈时钟信号，以及至少部分地基于反馈时钟调整缓冲的时钟信号的占空比 信号。 示例时钟发生器包括正向时钟路径，其被配置为提供来自时钟驱动器电路的延迟的输出时钟信号，并且还包括被配置为至少部分地基于延迟的输出时钟信号来提供反馈时钟信号的反馈时钟路径，用于 例如，对延迟输出时钟信号进行分频。 反馈时钟路径还被配置为至少部分地基于反馈时钟信号来控制缓冲的输入时钟信号的占空比调节。

公开(公告)号：US08433028B2

公开(公告)日：2013-04-30

申请号：US12795608

申请日：2010-06-07

申请人： John M. Khoury ,  Eduardo Viegas ,  Richard Beale

发明人： John M. Khoury ,  Eduardo Viegas ,  Richard Beale

IPC分类号： H03D3/24

CPC分类号： H03L7/0818

摘要： In an embodiment, a circuit includes a buffer circuit including a buffer input and an output terminal and a latency locked loop (LLL) circuit. The LLL circuit includes a signal input for receiving an input signal, a feedback input coupled to the output terminal, and a signal output coupled to the buffer input. The LLL circuit is configured to control a propagation delay between the signal input and the signal output to produce a substantially constant total delay from the signal input to the output terminal.

摘要翻译： 在一个实施例中，电路包括缓冲器电路，其包括缓冲器输入端和输出端子以及等待时间锁定环路（LLL）电路。 LLL电路包括用于接收输入信号的信号输入，耦合到输出端的反馈输入和耦合到缓冲器输入的信号输出。 LLL电路被配置为控制信号输入和信号输出之间的传播延迟，以从信号输入到输出端产生基本恒定的总延迟。