公开(公告)号：US20180102358A1

公开(公告)日：2018-04-12

申请号：US15497993

申请日：2017-04-26

Applicant: STMicroelectronics SA

Inventor： Philippe Galy ,  Sotirios Athanasiou

IPC: H01L27/02 ,  H01L27/12 ,  H01L29/45 ,  H01L27/06

CPC classification number: H01L27/0266 ,  H01L27/0629 ,  H01L27/1203 ,  H01L29/456

Abstract: An ESD protection device includes a MOS transistor connected between a first terminal and a second terminal and having a gate region, source/drain region and a well region electrically coupled by a resistive-capacitive circuit configured to control turn on of the MOS transistor in response to an ESD event. The resistive-capacitive circuit has a common part with at least one of the source, gate or drain regions of the MOS transistor and includes a capacitive element and a resistive element. A first electrode of the capacitive element is formed by the resistive element and a second electrode of the capacitive element is formed by at least a portion of a semiconductor film within which the source/drain region is formed.

公开(公告)号：US20180061833A1

公开(公告)日：2018-03-01

申请号：US15804669

申请日：2017-11-06

Applicant: STMicroelectronics SA

Inventor： Philippe Galy ,  Sotirios Athanasiou

IPC: H01L27/092 ,  H01L29/786 ,  H01L27/12 ,  H01L21/8238 ,  H01L21/84 ,  H01L23/528 ,  H01L29/08 ,  H01L29/10 ,  H01L29/165

CPC classification number: H01L27/092 ,  H01L21/8238 ,  H01L21/823871 ,  H01L21/84 ,  H01L23/528 ,  H01L27/1203 ,  H01L29/0847 ,  H01L29/1033 ,  H01L29/165 ,  H01L29/66772 ,  H01L29/78603 ,  H01L29/78615 ,  H01L29/78648 ,  H01L29/78654

Abstract: A substrate contact land for a first MOS transistor is produced in and on an active zone of a substrate of silicon on insulator type using a second MOS transistor without any PN junction that is also provided in the active zone. A contact land on at least one of a source or drain region of the second MOS transistor forms the substrate contact land.

公开(公告)号：US09905565B1

公开(公告)日：2018-02-27

申请号：US15464537

申请日：2017-03-21

Applicant: STMicroelectronics SA

Inventor： Hassan El Dirani ,  Yohann Solaro ,  Pascal Fonteneau

IPC: H01L27/108 ,  H01L29/06 ,  H01L29/08 ,  H01L29/78 ,  G11C11/409

CPC classification number: H01L27/10802 ,  G11C11/409 ,  H01L27/1203 ,  H01L29/0649 ,  H01L29/0847 ,  H01L29/407 ,  H01L29/7831 ,  H01L29/7841

Abstract: A microelectronic component is capable of being used as a memory cell. The component includes a semiconductor layer resting on an insulating layer and including a doped source region of a first conductivity type, a doped drain region of a second conductivity type, and an intermediate region, non-doped or more lightly doped, with the second conductivity type, than the drain region, the intermediate region including first and second portions respectively extending from the drain region and from the source region. An insulated front gate electrode rests on the first portion. A first back gate electrode and a second back gate electrode are arranged under the insulating layer, respectively opposite the first portion and the second portion.

公开(公告)号：US20180047440A1

公开(公告)日：2018-02-15

申请号：US15461979

申请日：2017-03-17

Applicant: STMicroelectronics SA

Inventor： Faress Tissafi Drissi

IPC: G11C11/419

CPC classification number: G11C11/419 ,  G11C2207/2263

Abstract: An autocorrective writing to a multiport static random access memory device is performed on at least one multiport static random access memory cell circuit. A first datum is written to the multiport static random access memory cell circuit and a second datum stored in the circuit is read from the multiport static random access memory cell subsequent to writing. The first and second data are compared. In response to the results of that comparison, an operation to rewriting the first datum to the circuit along with application of a write assist mechanism is selectively performed.

公开(公告)号：US20180038907A1

公开(公告)日：2018-02-08

申请号：US15468798

申请日：2017-03-24

Applicant: STMicroelectronics (Crolles 2) SAS ,  STMicroelectronics SA

Inventor： Vincent Huard ,  Chittoor Parthasarathy

IPC: G01R31/28

CPC classification number: G01R31/2858 ,  G01R31/2856 ,  G01R31/2884 ,  G01R31/2896

Abstract: A system-on-a-chip includes an integrated circuit and an estimation circuit. The estimation circuit operates to acquire at least one physical parameter representative of the use of the integrated circuit and determine an instantaneous state of aging of the integrated circuit as a function of the at least one physical parameter. A margin of use of the integrated circuit is then calculated by comparing the instantaneous state of aging with a presumed state of aging.

公开(公告)号：US09881928B2

公开(公告)日：2018-01-30

申请号：US15413497

申请日：2017-01-24

Applicant: STMicroelectronics SA

Inventor： Stéphane Denorme ,  Philippe Candelier

IPC: H01L27/112 ,  H01L21/84 ,  H01L23/525 ,  H01L27/12 ,  H01L21/28 ,  H01L29/40 ,  H01L29/49 ,  H01L29/66 ,  H01L21/762 ,  H01L29/06 ,  H01L21/8234 ,  H01L27/06

CPC classification number: H01L27/11206 ,  H01L21/28052 ,  H01L21/28097 ,  H01L21/7624 ,  H01L21/823418 ,  H01L21/84 ,  H01L23/5252 ,  H01L27/0629 ,  H01L27/1203 ,  H01L29/0649 ,  H01L29/401 ,  H01L29/4933 ,  H01L29/4975 ,  H01L29/66181 ,  H01L29/66507 ,  H01L29/6653 ,  H01L29/66545 ,  H01L29/6656 ,  H01L29/66628 ,  H01L2924/0002 ,  H01L2924/00

Abstract: An integrated circuit includes a silicon-on-insulator substrate that includes a semiconductor film located above a buried insulating layer. A first electrode of a silicide material overlies the semiconductor film. A sidewall insulating material is disposed along sidewalls of the first electrode. A dielectric layer is located between the first electrode and the semiconductor film. A second electrode includes a silicided zone of the semiconductor film, which is located alongside the sidewall insulating material and extends at least partially under the dielectric layer and the first electrode. The first electrode, the dielectric layer and the second electrode form a capacitor that is part of a circuit of the integrated circuit.

公开(公告)号：US20180005889A1

公开(公告)日：2018-01-04

申请号：US15632878

申请日：2017-06-26

Applicant: STMicroelectronics (Grenoble 2) SAS ,  STMicroelectronics SA ,  Commissariat A L'Energie Atomique et aux Energies Alternatives

Inventor： Didier Campos ,  Benoit Besancon ,  Perceval Coudrain ,  Jean-Philippe Colonna

IPC: H01L21/78 ,  H01L23/373 ,  H01L23/00 ,  H01L21/56 ,  H01L21/683 ,  H01L23/29 ,  H01L21/782

CPC classification number: H01L21/78 ,  H01L21/56 ,  H01L21/6836 ,  H01L21/782 ,  H01L23/29 ,  H01L23/36 ,  H01L23/373 ,  H01L23/562 ,  H01L2224/16225 ,  H01L2224/73204 ,  H01L2224/97 ,  H01L2924/15174 ,  H01L2924/15311 ,  H01L2924/18161

Abstract: Electronic devices are manufactured using a collective (wafer-scale) fabrication process. Electronic chips are mounted onto one face of a collective substrate wafer. A collective flexible sheet made of a heat-conductive material comprising a layer containing pyrolytic graphite is fixed to extend over a collective region extending over the electronic chips and over the collective substrate wafer between the electronic chips. The collective flexible sheet is then compressed. A dicing operation is then carried out in order to obtain electronic devices each including an electronic chip, a portion of the collective plate and a portion of the collective flexible sheet.

公开(公告)号：US09810823B2

公开(公告)日：2017-11-07

申请号：US15357871

申请日：2016-11-21

Applicant: STMicroelectronics SA ,  STMicroelectronics (Crolles 2) SAS ,  Commissariat A L'Energie Atomique et aux Energies Alternatives

Inventor： Romain Girard Desprolet ,  Sandrine Lhostis ,  Salim Boutami

IPC: H01Q15/02 ,  G02B5/20 ,  H01L27/146

CPC classification number: G02B5/208 ,  G02B5/20 ,  G02B5/204 ,  H01L27/1462 ,  H01L27/14621 ,  H01L27/14645 ,  H01L27/14649

Abstract: An infrared high-pass plasmonic filter includes a copper layer interposed between two layers of a dielectric material. An array of patterned openings extend through the copper layer and are filled with the dielectric material. Each patterned opening is in the shape of a greek cross, with the arms of adjacent patterns being collinear. A ratio of the width to the length of each arm is in the range from 0.3 to 0.6, and the distance separating the opposite ends of arms of adjacent patterns is shorter than 10 nm.

公开(公告)号：US20170288059A1

公开(公告)日：2017-10-05

申请号：US15230699

申请日：2016-08-08

Applicant: STMicroelectronics SA

Inventor： Sotirios Athanasiou ,  Philippe Galy

IPC: H01L29/78 ,  H01L23/528 ,  H01L21/84 ,  H01L27/12

CPC classification number: H01L29/7838 ,  H01L21/743 ,  H01L21/84 ,  H01L23/528 ,  H01L27/1203 ,  H01L29/41758 ,  H01L29/4238 ,  H01L29/66772 ,  H01L29/78 ,  H01L29/78615

Abstract: An integrated electronic device includes a semiconductive film above a buried insulating layer that is situated above a supporting substrate. An active zone is delimited within the semiconductive film. A MOS transistor supported within the active zone includes a gate region situated above the active zone. The gate region includes a rectilinear part situated between source and drain regions. The gate region further includes a forked part extending from the rectilinear part. A raised semiconductive region situated above the active zone is positioned at least partly between portions of the forked part. A substrate contact for the transistor is electrically coupled to the raised semiconductive region.

公开(公告)号：US20170287806A1

公开(公告)日：2017-10-05

申请号：US15451862

申请日：2017-03-07

Applicant: STMicroelectronics (Crolles 2) SAS ,  STMicroelectronics SA ,  Commissariat A L'Energie Atomique et aux Energies Alternatives

Inventor： Rafael Augusto Prieto Herrera ,  Jean-Philippe Colonna ,  Perceval Coudrain

IPC: H01L23/367 ,  H01L23/373 ,  H01L23/00 ,  H01L23/498 ,  H01L23/31

CPC classification number: H01L23/3672 ,  H01L23/3185 ,  H01L23/373 ,  H01L23/3736 ,  H01L23/4334 ,  H01L23/49816 ,  H01L24/16 ,  H01L2224/16225 ,  H01L2224/16227 ,  H01L2224/73253 ,  H01L2224/97 ,  H01L2924/15311 ,  H01L2924/1816 ,  H01L2924/18161 ,  H01L2224/81

Abstract: An electronic device includes a support and a component in the form of an integrated circuit chip having a rear face mounted above a front face of the support and a front face opposite its rear face. A block is provided for at least partially encapsulating the component above the front face of the support. The device also includes at least one thermal dissipation member having a flexible sheet having at least two portions folded onto one another while forming at least one fold between them, these portions facing one another at least partly.